NetTimeLogic’s DCF Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a DCF signal encoded as PWM. The encoding scheme is the one of the DCF77 sender near Frankfurt, Germany. The whole encoding, algorithms and calculations are implemented in the core, no CPU is required.
NetTimeLogic GmbH
Key Features
- DCF Slave Clock
- Supports DCF-77 format
- Optional Signal Filter
- DCF decoding and time format conversion
- DCF supervision
- Input delay compensation
- Air propagation delay compensation
- Additional seconds correction to convert between UTC and TAI time (or any other time base)
- AXI4 Light register set or static configuration
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Intertop | ISPCS |
| Latest Quartus Version Supported | 25.1.0 |
| OS Support | Not required |
| Development Language | VHDL |
Source Code
Ordering Information
NTL_DCF_SLAVE
from Direct
Documentation & Resources
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