.webp){kind=small}
The Adjustable Clock from NetTimeLogic is an adjustable counter clock with nanosecond resolution (second and nanosecond format), which is used by all other cores from NetTimeLogic but can also be used as standalone core. It contains a hardware implemented PI servo loop for smooth adjustment of frequency and phase, which can be adjusted in parallel and individual. It has multiple adjustment inputs which are multiplexed to define the source of synchronization and an addvance holdover calculation for situations where no synchronization source is available.
NetTimeLogic GmbH
Key Features
- 32 bit second and 32 bit nanosecond counter clock with fractional extention
- 1 millisecond pulse generator aligned with the counter clock
- Allows non-integer clock periods
- Multiplexing of multiple adjustment inputs
- Evenly spread offset and drift correction (offset might be set hard in case of large offsets), hard setting of time possible
- Individual hardware only PI servo loops for offset and drift correction (PI parameters individually configurable)
- Runtime changeable PI servo parameters
- Offset correction: min 1/2^16 ns / s, max 0.5 s/s, Drift correction: min 1/2^16 ns / s, max 0.05 s/s
- Conversion of fractional adjustments into even spread clock adjustments
- Optional Advanced Holdover Correction calculation as average of adjustments over a configurable window plus aging compensation
- Optional outlier filter, rate limiter
- AXI4 Light register set or static configuration, can represent a PHC clock in Linux
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Intertop | ISPCS, IIC |
| Latest Quartus Version Supported | 25.1.0 |
| OS Support | Linux |
| Development Language | VHDL |
Source Code, Driver
Ordering Information
NTL_CLK_CLOCK
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Access
View Sub-Segments
Aerospace
View Sub-Segments
Broadcast
View Sub-Segments
Data Center Cloud (Public, Private, Hybrid)
View Sub-Segments.svg?h=0&v=8a74a614-b7ba-4604-ad78-f0827c6a3874&itok=rVWXlOCO)
Defense
View Sub-Segments
Government
View Sub-SegmentsImage
Test
View Sub-Segments
Transportation
View Sub-SegmentsTransportation
Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)
