The Signal Generator from NetTimeLogic is a clock aligned pulse and pattern (PWM) generator with nanosecond resolution (second and nanosecond format). It uses NetTimeLogic's Adjustable Clock core as source for time driven signal generation. It allows single, multi (configurable) and continuous pulse generation with configurable polarity, start time, interval and duty cycle.
NetTimeLogic GmbH
Key Features
- Pulse Width Modulated (PWM) signal generation
- 32 bit second and 32 bit nanosecond start time, pulse width and period
- Configurable polarity
- Output delay compensation
- Automatic disabling of generation on time jumps
- Repeat count
- AXI4 Light register set or static configuration
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Intertop | ISPCS, IIC |
| Latest Quartus Version Supported | 25.1.0 |
| OS Support | Linux |
| Development Language | VHDL |
Source Code, Driver
Ordering Information
NTL_CLK_SIGNAL_GEN
from Direct
Documentation & Resources
Market Segment and Sub-Segments
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Automotive (Passenger Vehicles)
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Transportation Infrastructure (non-charging)