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The ST 2059 PTP core is an FPGA IP core that generates timing and clock signals according to the SMPTE ST 2059 standard defined by the Society of Motion Picture and Television Engineers. These deterministic timing signals can be used to time synchronize audio and video systems to a SMPTE ST2059 (PTP) grandmaster. The IP core provides broadcast and professional AV equipment the ability to support deterministic generation of timing (signals) for video and audio systems.
Nextera Video
Key Features
- Fast locking performance
- Generation of HH:MM:SS:FF Time Code,
- Generation of multiple programmable output reference clock and sync signals
- JT-NM Tested – Implementation is successfully tested during multiple SMPTE and VSF interoperability testing events, earning all possible badges
- Supports the use of non-PTP aware switches, as well as PTP-aware transparent and boundary clocks
- The AIP-ST2059 core is network speed independent, so it can be used in 1G, 10G, 25G and 100G Ethernet networks.
Offering Brief
Offering Brief
| Device Family | Agilex® 5 FPGA D-Series, Agilex® 7 FPGA F-Series |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | Yes |
| Compliance | Yes |
| Intertop | JT-NM Tested |
| Latest Quartus Version Supported | 24.1.0 |
| Development Language | Encrypted VHDL |
Reference design, drivers, daemons, software, web GUI
Ordering Information
DK-SI-AGI027FD
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Aerospace
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Broadcast
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Government
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