CoaXPress Host IP Core

Overview Key Features Offering Brief What's Included Ordering Information Markets

Sensor to Image GmbH

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Sensor to Image offers a set of IP cores and a development framework to build FPGA-based receivers using the CoaXPress interface. Compact and customizable, they support speeds from 1 Gbps up to 100 Gbps, and are delivered as working reference design.

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Key Features

CoaXPress 2.1 IP for host/receiver applications
Support of multiple connections

Offering Brief

Device Family	Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Arria® 10 GX FPGA, Cyclone® 10 GX FPGA
Offering Status	Production
Design Examples Available	Yes
Compliance	Yes
Intertop	JIIA Compliance Test
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted VHDL, VHDL

Reference Design for Altera Evaluation Kit

CXP Interface FMC card

Documentation

Training

Support

Ordering Information