USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

System Level Solutions, Inc

Select

USB 2.0 Device, Software Enumeration FIFO interface (USB20SF) IP Core is a FIFO based USB 2.0 device core with 32-bit Avalon interface and ULPI interface support. Avalon interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.

View Partner Website

Partner Product Page

Contact Now

Contact System Level Solutions, Inc

We collect personal information from you, including identifiers and geolocation data, to enhance your experience, provide customer support, and analytics. We may share this data with third-party providers. For more information, please see our Privacy Policy.

LeadSource

ASAP Account ID

Record Type Name

Key Features

Supports LS (1.5 Mbps), FS (12 Mbps) and HS (480 Mbps) modes
Supports Control, Bulk, Interrupt and Isochronous transfers
Capable to support up to 31 endpoints (1 default control endpoint +15 IN/OUT endpoints)
Supports software configurable endpoints
Allows you to configure endpoints based on your needs
Supports Suspend, Resume and Remote Wakeup features
Supports UTMI + Low Pin interface (ULPI) interface
Supports Test modes (Test J, Test K, Test SE0 NAK, Test Packet)
The core has been optimized for popular FPGA devices, and its functionality has been verified on the real hardware
Ready to use component
Software controlled CONTROL endpoint
Simple FIFO interface to transfer data over non-control endpoint

Offering Brief

Device Family	Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	Yes
Latest Quartus Version Supported	25.1.0
OS Support	Windows,Linus
Development Language	Encrypted Verilog, Verilog

Encrypted IP Core

Reference Design

Reference Documents

Demo

HAL Driver

Ordering Information