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TES Warping Engine is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory to memory or memory to AXI4 Stream. Applications are for example pre-warping for projection on head-up displays (HUDs) or fisheye-correction of camera images. The image transformation is controlled via a highly compressed Look Up Table (LUT) allowing arbitrary transformations. The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Altera Avalon bus interface at different bus width.
TES Electronic Solutions GmbH
Key Features
- Image warping / transformation
- Scaling
- Cropping
- Output streaming
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® III LS FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GT FPGA, Stratix® IV GX FPGA, Stratix® V E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Evaluation License | Yes |
| Latest Quartus Version Supported | 24.1.0 |
| OS Support | bare metal,Linux |
| Development Language | C/C++, Encrypted VHDL, VHDL |
QSys component
baremetal driver source code
Tools for LUT generation (also as source code)
Documentation
Ordering Information
Warping Engine
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Aerospace
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ASIC Proto
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Consumer
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Defense
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Industrial
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Medical
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