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Extreme speed AES256-GCM core implements the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with up to 800G linerate. AES-GCM is a widely used cryptographic algorithm for Authenticated Encryption with Associated Data (AEAD) purposes, providing both data confidentiality and authenticity.
Xiphera Ltd.
Key Features
- High Security: XIP1113E implements AES256-GCM authenticated encryption as defined in the NIST standards FIPS PUB 197 [1] and Special Publication 800-38D [2], and offers a security level of 256 bits.
- Extremely High Throughput: XIP1113E offers extremely high throughput for a single stream of data as it processes one 32/64/128-byte block per clock cycle and has a high maximum clock frequency. The IP cores of XIP1113E achieve throughputs of hundreds of Gbps depending on the target FPGA.
- Constant Latency: XIP1113E offers constant latency for every data block and has a deter- ministic latency that facilitates an easy integration to various systems.
- Secure Design: XIP1113E executes encryption and decryption in constant time (that is, in- dependent of the value of the key), and therefore provides full protection against timing side-channel attacks.
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV GX FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Compliance | Yes |
| Latest Quartus Version Supported | 25.1.1 |
| Development Language | Encrypted Verilog, Verilog |
Encrypted RTL or source code
Sample synthesis scripts
Instantiation file
Detailed datasheet and integration guide
Optional netlist
Ordering Information
XIP1113E
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