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Compact SHA-3 IP core provide versatile functionality for various applications, from data integrity verification to password security. Xiphera’s SHA-3 IP cores support SHA3-224, SHA3-256, SHA3-384, SHA3-512, and related functions such as SHAKE, cSHAKE, KMAC, TupleHash, and ParallelHash.
Xiphera Ltd.
Key Features
- Minimal Resource Requirements: XIP3030C requires 1394 ALMs with Altera Cyclone® 10 LP or 1003 6-input LUTs with AMD Zynq-7000® and use only some internal memory blocks in a typical FPGA implementation.
- Versatile Algorithm Support: XIP3030C supports SHA-3-224/256/384/512, SHAKE-128/256, and cSHAKE-128/256. That is, XIP3030C covers all algorithms defined in [1] and also all algorithms included in [2] are supported via cSHAKE.
- Secure Architecture: The execution time of XIP3030C is independent of the input values and, consequently, provides full protection against timing-based side-channel attacks.
- Standard Compliance: XIP3030CiscompliantwithFIPS202[1] andSP800-185[2]. XIP3030C can be used as a part of numerous systems and protocols that require SHA-3 or its derivatives.
- Easy Integration: The 64-bit interface of XIP3030C supports easy integration to various systems.
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Latest Quartus Version Supported | 25.1.1 |
| Development Language | Encrypted VHDL, VHDL |
Encrypted RTL or source code
Sample synthesis scripts
Optional netlist
Instantiation file
Comprehensive simulation test bench, scripts & guide
Detailed datasheet and integration guide
Ordering Information
XIP3030C
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