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IP-Maker's powerful IPM-BCH is based on the BCH algorithm. The IP-Maker BCH Encoder/Decoder is full-featured with multiple parameters to fit your own needs in FPGA and SoC designs. In fact IPM-BCH Encoder/Decoder is fully configurable, allowing to it reach the best latency or the smallest footprint. Customizable parameters include: Chien Search algorithm, Galois Field, and data path.
IP-Maker
Key Features
- Customizable Data path
- Customizable block size
- Customizable Galois Field
- Customizable number of error correction
- Customizable trade off latency and throughput
Offering Brief
Offering Brief
| Device Family | Arria® 10 GX FPGA, Arria® 10 SX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Design Examples Available | Yes |
| Latest Quartus Version Supported | 24.1.1 |
| Development Language | Verilog |
IP core in source code customized for the need
Simulation environment
Documentation
Support/maintenance
Ordering Information
IPM-BCH
from Direct
$15000.00
Documentation & Resources
Market Segment and Sub-Segments
Access
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Aerospace
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ASIC Proto
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Consumer
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