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IP-Maker's powerful IPM-LDPC is based on the LDPC algorithm. The IP-Maker IPM-LDPC Encoder/Decoder is full-featured with multiple parameters to fit your own needs in FPGA and SoC designs. In fact IPM-LDPC Encoder/Decoder is fully configurable, allowing to it reach the best latency or the smallest footprint. Customizable parameters include: number of check per bit, number per iteration, block size, bit error rate.
IP-Maker
Key Features
- Adaptable BER
- Up to 6 checks per bit
- Customizable data path
Offering Brief
Offering Brief
| Device Family | Arria® 10 GT FPGA, Arria® 10 GX FPGA |
|---|---|
| Offering Status | Development |
| Integrated Testbench | Yes |
| Latest Quartus Version Supported | 24.1.1 |
| Development Language | Verilog |
IP core in source code or in netlist
Simulation environment
Documentation
Support/maintenance
Ordering Information
IPM-LDPC
from Direct
$0.00
