The 10G/100G TCP/IP Offload Engine (TOE) IP Core is a high-performance, scalable, and fully synthesizable hardware accelerator that offloads complete TCP/IP stack processing from the host CPU, enabling deterministic, wire-speed data transmission with ultra-low latency. Designed for FPGA and ASIC implementations, it delivers full hardware-based TCP, IP, ARP, ICMP, and optional UDP processing, significantly reducing CPU utilization while maintaining consistent performance under heavy traffic loads. Supporting sustained line-rate throughput at both 10G and 100G, the core efficiently manages thousands of concurrent sessions with configurable memory architecture, including external DDR or HBM integration for large buffer and connection table support. Its optimized pipeline architecture minimizes jitter and ensures predictable round-trip latency, making it ideal for high-frequency trading (HFT), data center acceleration, SmartNICs, storage over TCP (iSCSI, NVMe-oF),...
Qbit Labs Incorporation
The 10G/100G TCP/IP Offload Engine (TOE) IP Core is a high-performance, scalable, and fully synthesizable hardware accelerator that offloads complete TCP/IP stack processing from the host CPU, enabling deterministic, wire-speed data transmission with ultra-low latency. Designed for FPGA and ASIC implementations, it delivers full hardware-based TCP, IP, ARP, ICMP, and optional UDP processing, significantly reducing CPU utilization while maintaining consistent performance under heavy traffic loads. Supporting sustained line-rate throughput at both 10G and 100G, the core efficiently manages thousands of concurrent sessions with configurable memory architecture, including external DDR or HBM integration for large buffer and connection table support. Its optimized pipeline architecture minimizes jitter and ensures predictable round-trip latency, making it ideal for high-frequency trading (HFT), data center acceleration, SmartNICs, storage over TCP (iSCSI, NVMe-oF), telecom infrastructure, and high-performance network appliances. With flexible host interfaces such as PCIe and AXI, advanced congestion and flow control mechanisms, hardware retransmission handling, checksum offload, and robust reliability features, the TOE IP Core enhances system throughput, reduces power consumption, lowers total cost of ownership, and accelerates time-to-market for next-generation high-bandwidth networking solutions.
Key Features
- Full TCP/IP Stack Offload: Hardware implementation of Layer 3 (IP) and Layer 4 (TCP/UDP) for maximum efficiency.
- Line Rate Throughput at 10G & 100G: Optimized architecture for deterministic performance at wire speed.
- Configurable Session Support: Supports thousands of simultaneous TCP/UDP connections with dynamic resource allocation.
- Checksum Generation and Verification: Full support for TCP, UDP, and IP checksum operations.
- Zero-Copy Data Path: Supports Direct Memory Access (DMA) for ultra-low latency and minimal CPU intervention.
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| OS Support | Linux (Enterprise & Embedded), Windows Server |
| Development Language | Encrypted Verilog, Verilog |
Synthesizable RTL source code
Directed/random/constrained-random sequences covering LTSSM, configuration, link training, FLIT mode, error injection (FEC/CRC scenarios), power states, reset.
Embedded firmware / low-level SW
Software integration guide
Full design documentation
FPGA bitstream/prototyping support
Ordering Information
QB-IP-Ethernet-10G/100G-1
from Direct
$0.00
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