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Turbo Convolutional Codes (TCC) are an advanced class of Forward Error Correction (FEC) techniques designed to improve the reliability of digital communication systems operating in noisy or bandwidth-limited environments. By combining multiple convolutional encoders with an interleaver and using an iterative decoding process, TCCs can approach the theoretical Shannon limit, enabling highly efficient error correction with minimal signal degradation. This makes them particularly valuable in high-performance communication systems where data accuracy and link reliability are critical. Due to their exceptional error-correction capability, Turbo Convolutional Codes are widely used in modern communication standards such as 3G and 4G LTE networks, as well as in satellite communications, aerospace systems, and defense applications that require robust and dependable data transmission.
Qbit Labs Incorporation
Key Features
- Configurable Code Rates: Supports variable rates like 1/3, 1/2, 2/3, and custom rates using puncturing techniques.
- Iterative Soft-Decision Decoding: Implements MAP or Log-MAP decoding algorithms for near-optimal error correction.
- Scalable Block Size Support: Handles fixed and variable block sizes for flexible application across standards.
- High Throughput Architecture: Pipelined and parallelized for multi-Gbps throughput on FPGA/ASIC platforms.
- Rate Matching and Interleaving: Built-in support for matrix-based interleaving, de-interleaving, and bit rearrangement.
- Low Bit Error Rate (BER): Strong correction in high noise environments, suitable for deep space and defense links.
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
Synthesizable RTL source code
Directed/random/constrained-random sequences covering LTSSM, configuration, link training, FLIT mode, error injection (FEC/CRC scenarios), power states, reset
Embedded firmware / low-level SW
Software integration guide
Full design documentation
Ordering Information
QBL-IP-FEC-TCC
from Direct
$0.00
Market Segment and Sub-Segments
Aerospace
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Defense
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Government
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Wireless
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5G/ 6G Radio
AI-RAN
Baseband
DAS/repeater/RIS
FWA/backhaul
NTN/Fixed Wireless
RDU
xhaul Hub