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Turbo Product Codes (TPC) are advanced Forward Error Correction (FEC) techniques designed to provide high reliability in digital communication systems operating in noisy or interference-prone environments. TPCs are constructed by combining two or more block codes in a product-code structure, typically arranged in rows and columns, which allows errors to be detected and corrected iteratively. This structure enables efficient decoding with strong error-correcting performance while maintaining moderate computational complexity compared to other high-performance coding schemes. Due to their ability to achieve very low bit-error rates (BER) and maintain data integrity over long-distance or high-noise channels, Turbo Product Codes are widely used in satellite communications, deep-space telemetry, aerospace systems, and defense-grade communication networks where reliable data transmission is critical.
Qbit Labs Incorporation
Key Features
- Configurable Code Rates and Block Sizes: Supports multiple configurations, including square and rectangular matrix arrangements.
- High Coding Gain: Excellent BER performance over AWGN and fading channels, suitable for low-SNR links.
- Soft-Decision Decoding Support: Implements efficient Chase and Iterative decoding algorithms for enhanced correction.
- Parallel and Pipelined Architecture: Achieves multi-Gbps throughput with low decoding latency on modern hardware.
- Interface Flexibility: Standard interfaces like AXI4-Stream or custom wrappers for seamless integration.
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
Synthesizable RTL source code
Directed/random/constrained-random sequences covering LTSSM, configuration, link training, FLIT mode, error injection (FEC/CRC scenarios), power states, reset
Embedded firmware / low-level SW
Software integration guide
Full design documentation
Ordering Information
QBL-IP-FEC-TPC
from Direct
$0.00
Market Segment and Sub-Segments
Aerospace
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Defense
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Government
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