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SHA2 IP core is an optimized and efficient implementation of the SHA-2 cryptographic hash family, compliant with the FIPS 180-4 standard. The core supports SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, and SHA-512/256 algorithms, enabling flexible and secure hashing for a wide range of applications. Designed for FPGA and embedded systems, it accelerates secure communication, password authentication, and blockchain data integrity while reducing CPU workload. When combined with Design Gateway’s networking and storage IPs, it enables the development of secure, high-performance, and efficient applications.
DesignGateway Co., Ltd.
Key Features
- Supports SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, and SHA-512/256 algorithms.
- Accepts input message lengths up to 264-8 bits (SHA-224/256) and 2128-8 bits (SHA-384/512)
- High-performance architecture with only: (65 cycles per 64-byte block for SHA-224/256) (81 cycles per 128-byte block for SHA-384/512)
- Achieves throughput up to: (1.969 Gbps @ 250 MHz for SHA-256) (3.160 Gbps @ 250 MHz for SHA-512)
- User data interface: Utilizes a 32-bit AXI4 stream interface.
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA I-Series, Arria® 10 SX FPGA |
|---|---|
| Offering Status | Production |
| Design Examples Available | Yes |
| Demo | Yes |
| Latest Quartus Version Supported | 23.1.0 |
| Development Language | VHDL |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-SHA2-IP
from Direct
NET-SHA2-IP
from Macnica
NET-SHA2-IP
from Uniquest
Documentation & Resources
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