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WireGuard10G-IP core implements the complete WireGuard VPN protocol entirely in hardware, delivering full 10 Gbps line-rate encryption and decryption with no CPU load and no external memory required. It eliminates CPU overhead by performing the full Noise handshake, ChaCha20-Poly1305 encryption, X25519 key exchange, and BLAKE2s key derivation entirely in programmable logic. Proven with real WireGuard software interoperability testing on FPGA evaluation boards.
DesignGateway Co., Ltd.
Key Features
- 10 Gbps line-rate encryption and decryption with no CPU load and no external memory required
- Internal Handshake Support
- IPv4 Protocol Support without IP fragmentation
- Integrated UDP/IP and ARP Protocol Controllers
- Jumbo Frame Support
- User Data Interface: 64-bit AXI4-Stream
- Ethernet MAC Interface: 64-bit AXI4-Stream
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA I-Series |
|---|---|
| Offering Status | Development |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Verilog |
Encrypted IP core
Reference Designs Quartus Project
Ordering Information
NET-WireGuard10G-IP
from Direct
Documentation & Resources
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