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This course develops systematic and detailed understanding of the Altera FPGA device family and the Quartus Prime Pro ecosystem as applied to AI inference acceleration. Participants progress from FPGA fabric primitives (ALMs, DSP blocks, M20K SRAM, HBM2e) through the Agilex AI Tensor block architecture, memory subsystem design, AXI4 interfaces, and structured performance benchmarking methodology. The course bridges the conceptual gap between ML model characteristics and FPGA hardware resources, providing the architectural vocabulary and toolchain fluency. Extensive use of Quartus Prime Pro, Platform Designer, Signal Tap, and the Agilex 5 development kit ensures participants leave with practical device-level competency.
FPGA Authority
Key Features
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series |
|---|---|
| Offering Status | Production |
| Prerequisites | FPGA Authority's “ML/AI Essentials for Hardware Engineers” course or an equivalent foundational ML knowledge |
| Languages | English |
| Target Audience | Hardware and Software Engineers, FPGA Designers, SoC Developers, Verification Engineers, System Architects, Managers |
| Duration | 2 Days |
| Hands On Lab | True |
| OS Support | Windows,Linux |
PDF of slides, lab manual and lab files
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FPGA Architecture and AI Acceleration
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