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The Synaptic Labs xSPI Multiple Bus Memory Controller (xSPI MBMC) is a silicon-proven memory controller IP supporting a broad range of JEDEC xSPI and xSPI-like memories, including HyperRAM™, HyperFlash™, Octal NOR Flash, Octal PSRAM, Xccela® PSRAM, and emerging xSPI MRAM devices. The controller has been physically tested across multiple FPGA families and memory vendors, helping customers reduce development risk and accelerate time to market.
Synaptic Laboratories Ltd
Key Features
- Silicon-proven IP used in industrial, communications, aerospace, defense, and embedded applications
- Support for multiple memory protocols through a unified controller architecture
- High-performance DDR operation
- Compact FPGA footprint
- Easy integration into Intel FPGA designs
- Comprehensive technical support from memory and FPGA experts
- Physically qualified with memory devices from leading memory vendors
- Supports both memory-mapped and high-bandwidth applications
- Reduces project risk and shortens development schedules
- Support for x8/x16
- Supports HyperRAM devices from Infineon, SSI,Winbond
- Supports HyperFlash devices from Infineon and ISSI
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® V E FPGA, Stratix® 10 AX FPGA |
|---|---|
| Offering Status | Production |
| Demo | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Intertop | All xSPI memory devices from all vendors |
| Latest Quartus Version Supported | 24.3.1 |
| OS Support | Linux, Windows |
| Development Language | C/C++, Encrypted Verilog |
Encrypted IP Core, Documentation, Reference Project.
Ordering Information
SLL-xSPI-MBMC
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Consumer
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Data Center Cloud (Public, Private, Hybrid)
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