Advanced SoC System Design & Verification

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FPGA Authority

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This advanced course brings together all disciplines of Altera® SoC FPGA design into a comprehensive system design and verification experience. Students tackle the full SoC design cycle including system partitioning, hardware architecture, FPGA RTL implementation, Linux BSP, software integration, and system level verification. Students work with the Altera Agilex and Cyclone V SoC platforms to explore hard processor system (HPS) architecture, AXI interconnect design, custom IP integration, and high performance DMA data paths. The course leverages UVM based verification methodology and advanced formal verification techniques alongside physical hardware bring up and software integration.

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Key Features

Offering Brief

Device Family	Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA
Offering Status	Production
Prerequisites	Experience with Quartus Prime, exposure to UVM or SystemVerilog verification concepts, familiarity with embedded C programming and cross compilation toolchains and an understanding of ARM Cortex A processor architecture.
Languages	English
Target Audience	Hardware and Software Engineers, FPGA Designers, SoC Developers, Verification Engineers, System Architects
Duration	2 Days
Hands On Lab	True
OS Support	Windows,Linux

PDF of slides, lab manual and lab files where applicable

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