DSP on FPGAs: RTL to IP

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FPGA Authority

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This course teaches engineers how to design, implement, verify, and optimize high performance DSP systems on Altera FPGA devices using both hand coded RTL HDL and Altera's production grade IP cores. It is the second course in the FPGA Authority Progressive DSP Training Program and assumes that participants have completed the “DSP Fundamentals & Python Prototyping” course or possess equivalent DSP theory knowledge. All DSP theory, sampling, filter design, FFT mathematics, adaptive filtering, is assumed as prior knowledge. The course opens at the RTL level and focuses entirely on hardware implementation concerns: how to map DSP algorithms to Altera DSP blocks and memory resources, how to write synthesis efficient HDL pipelines, how to configure Altera IP cores, and how to close timing on multi clock DSP systems.

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Key Features

Offering Brief

Device Family	Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA
Offering Status	Production
Prerequisites	FPGA Authority “DSP Fundamentals & Python Prototyping” course completion, or equivalent DSP theory knowledge. Basic HDL experience and digital logic design fundamentals.
Languages	English
Target Audience	Hardware and Software Engineers, FPGA Designers, Verification Engineers, System Architects
Duration	2 Days
Hands On Lab	True
OS Support	Windows,Linux

PDF of slides, lab manual and lab files where applicable

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