HLS, OpenCL, and RTL for AI Inference and Acceleration

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FPGA Authority

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This advanced course develops the skills to design, optimize, and integrate custom AI inference accelerator kernels using Altera HLS Compiler Pro, the Altera FPGA SDK for OpenCL, and RTL/SystemVerilog on Altera FPGAs. Participants work at the lowest level of the acceleration stack: implementing Conv2D, GEMM, depth-wise separable convolution, multi-head attention, and activation function kernels from scratch; applying advanced HLS optimization techniques (pipelining, unrolling, dataflow, memory partitioning); designing systolic array architectures; implementing Transformer and attention mechanisms in hardware; and integrating all components into complete Platform Designer systems through AXI4 and AXI4-Stream interfaces.

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Key Features

Offering Brief

Device Family	Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA
Offering Status	Production
Prerequisites	FPGA Authority “FPGA Architecture and AI Acceleration” and “ML/AI Essentials” courses. proficiency in C/C++ programming, working knowledge of Verilog or SystemVerilog at the RTL design level and familiarity with FPGA synthesis and timing closure.
Languages	English
Target Audience	Hardware and Software Engineers, FPGA Designers, Verification Engineers, System Architects,
Duration	2 Days
Hands On Lab	True
OS Support	Windows,Linux

PDF of slides, lab manual and lab files where applicable

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