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The SHA3-IP core is a highly efficient, pure-hardware hash engine that implements all six algorithms defined in the FIPS PUB 202 standard (SHA3-224, SHA3-256, SHA3-384, SHA3-512, SHAKE128, and SHAKE256) within a single integrated core. It provides ultra-high throughput exceeding 17.5 Gbps and allows dynamic algorithm selection at runtime. It is ideal for accelerating secure communications, data integrity, and authentication applications on Altera FPGAs without CPU overhead.
DesignGateway Co., Ltd.
Key Features
- Achieves over 17.5+ Gbps throughput @ 316 MHz
- Byte oriented implementation compatible with FIPS 202
- Customizable output length for SHAKE algorithm.
- Dynamic algorithm and output length selection at runtime using control interface
- Input/Output Data Interface: 64-bit AXI4-Stream
- 1344-bit Parallel Output Interface for single-cycle flat hash reading
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA I-Series, Arria® 10 SX FPGA |
|---|---|
| Offering Status | Development |
| Latest Quartus Version Supported | 23.1.0 |
| Development Language | Encrypted VHDL |
Comprehensive User Manual & Verification Guide
Free Evaluation Bitstream (available for rapid on-board testing prior to purchase)
Complete Reference Design & Demo Project (Quartus project files for supported FPGA development boards)
Ordering Information
NET-SHA3-IP
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Aerospace
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ASIC Proto
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Data Center Cloud (Public, Private, Hybrid)
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Defense
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Government
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Industrial
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Transportation
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Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)