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The Arasan I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Secondary Controller logic. The I3C bus is used for various sensors in the mobile/automotive system where the active controller transfers data and control between itself and various sensor devices. In some applications, the active controllers can handoff the controller role to the secondary controller on the bus. The Dual role IP joins the I3C bus as a secondary controller (as a target) and will request/accept the controller role. The IP core provides a 32bit AHB bus as application interface to configure and control the transfers. The controller manages the control signal to IO buffers during the active and standby mode
Arasan Chip Systems Inc
Key Features
- Capability to hot join the I3C bus with secondary controller logic Support for simple controller role request for the purpose of requesting or attempting to regain the controller role from the active controller Autonomously service certain standard CCCs sent by the active controller Standby controller mode specific register set for configuration and control via Extended capability register Optional support for generic read-type and write-type transactions sent by the active controller
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA E-Series |
|---|---|
| Offering Status | Production |
| Latest Quartus Version Supported | 26.1.0 |
| Development Language | Verilog |
. RMM compliant synthesizable RTL design in Verilog • Easy-to-use Test environment • Synthesis scripts • Technical documents • Validated with 3rd Party Host Controller VIP and available as an additional option
Ordering Information
ACS_DIP_I3C_Dual_Controller
from Direct
