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A two-wire sideband negotiates profile, rate, protocol, link settings and active lanes. Lane-ID exchange discovers reversed, shuffled and dead lanes, with clean peer-reset behavior and optional integration configuration. The customer receives sideband RTL and register contract; lane discovery/remapping integration; reset and negotiation behavior; reversed/shuffled/dead-lane test collateral. SystemVerilog peer-link IP with Agilex® 5 E-Series and Quartus Prime Pro 25.3.0 package/reference compatibility. Interface integration, timing and application acceptance are defined for the selected configuration. Scope, interfaces and acceptance criteria are agreed for the selected release.
Garmo Labs
Key Features
- Sideband RTL and register contract; Lane discovery/remapping integration; Reset and negotiation behavior; Reversed/shuffled/dead-lane test collateral
Offering Brief
Offering Brief
| Device Family | Agilex® 5 FPGA E-Series |
|---|---|
| Offering Status | Production |
| Latest Quartus Version Supported | 25.3.0 |
| Development Language | Other |
Sideband RTL and register contract; Lane discovery/remapping integration; Reset and negotiation behavior; Reversed/shuffled/dead-lane test collateral
Ordering Information
Contact Garmo Labs for a configuration-specific ordering reference.
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