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Ultra Ethernet Interconnect IP for AI Infrastructure

DynaNIC Semiconductors s.r.o.

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DYNANIC is developing a high-performance Ultra Ethernet (UE) interconnect IP designed for next-generation AI and HPC infrastructure.

Built on our proven 400G packet processing architecture, the solution brings Ultra Ethernet networking capabilities to programmable hardware, targeting efficient RDMA communication, congestion management, and scalable connectivity between AI compute nodes and clusters.

Our architecture is designed to handle demanding traffic patterns at wire speed, with particular focus on high throughput, low latency, and efficient utilization of network resources.

The solution is being developed on Altera FPGA platforms, with 400G Ultra Ethernet technology already demonstrated at AI Infra Summit 2026. Development continues toward broader protocol functionality and interoperability.

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Key Features

  • 400G+ Ultra Ethernet interconnect architecture
  • Wire-speed packet processing with efficient handling of demanding traffic patterns
  • RDMA communication support
  • Advanced congestion management
  • Scalable architecture for AI and HPC networking
  • Flexible implementation for evolving Ultra Ethernet requirements
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Offering Brief

Offering Brief

Device Family Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series
Offering Status Development
Evaluation License Yes
Demo Yes
Latest Quartus Version Supported 26.1.1
Development Language Encrypted VHDL, VHDL

Ultra Ethernet Interconnect IP Core

Integration and Customization Services

Ordering Information

DYNA-UE-IP

from Direct

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Market Segment and Sub-Segments

Data-Center-Cloud-252x228

Data Center Cloud (Public, Private, Hybrid)

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Data Center Cloud (Public, Private, Hybrid)

AI/HPC

Networking

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Data-Center-OEM-252x228

Data Center OEM (IHV, ISV, SI, VAR)

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Data Center OEM (IHV, ISV, SI, VAR)

AI/HPC

Networking

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