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INTERA Harrier Cognit is a high-throughput AI accelerator IP designed to deliver exceptional computing performance and energy efficiency for demanding Edge AI and TinyML workloads. Featuring a monolithic streaming architecture optimized for matrix-matrix operations, Harrier enables high-speed AI inference while minimizing latency and silicon overhead. Its highly scalable processing architecture supports matrix arrays starting at 8×8 processing elements and expanding to configurations such as 32×32, 32×64, and 64×64, providing flexibility for compute-intensive applications. Combining ultra-low-power operation with efficient on-device processing, Harrier addresses the requirements of intelligent industrial systems, advanced sensing, predictive maintenance, and smart security applications. Supported by INTERA’s open-source software suite and AI development frameworks, Harrier enables seamless integration and accelerated deployment of neural network models across ...
INTERA Group
INTERA Harrier Cognit is a high-throughput AI accelerator IP designed to deliver exceptional computing performance and energy efficiency for demanding Edge AI and TinyML workloads. Featuring a monolithic streaming architecture optimized for matrix-matrix operations, Harrier enables high-speed AI inference while minimizing latency and silicon overhead. Its highly scalable processing architecture supports matrix arrays starting at 8×8 processing elements and expanding to configurations such as 32×32, 32×64, and 64×64, providing flexibility for compute-intensive applications. Combining ultra-low-power operation with efficient on-device processing, Harrier addresses the requirements of intelligent industrial systems, advanced sensing, predictive maintenance, and smart security applications. Supported by INTERA’s open-source software suite and AI development frameworks, Harrier enables seamless integration and accelerated deployment of neural network models across next-generation intelligent edge devices.
Features • High-Performance Matrix-Matrix Acceleration (MxM) – Dedicated hardware acceleration for compute-intensive neural network operations. • Monolithic Streaming Architecture – Optimized dataflow processing for efficient, high-throughput AI inference. • Scalable Processing Architecture – Configurable processing arrays, starting at 8 × 8 (64 processing elements), scalable to 32 × 32, 32 × 64, 64 × 64 and larger configurations. • Ultra-Low-Power AI Processing – Designed for energy-efficient Edge AI and TinyML applications. • High Computational Throughput – Parallel matrix processing to accelerate demanding AI workloads. • Efficient Data Streaming – Minimizes unnecessary data transfers to improve processing efficiency. • Low-Latency AI Inference – Supports fast, real-time neural network execution. • Configurable Hardware Architecture – Adaptable processing capacity to meet application-specific performance requirements. • Optimized Silicon Utilization – Designed to balance processing performance, power consumption and silicon area. • Continuous AI Processing – Supports always-on embedded intelligence. • Neural Network Acceleration – Suitable for convolutional neural networks (CNNs) and other matrix-intensive AI workloads. • Flexible SoC Integration – Designed for incorporation into embedded processors and semiconductor SoC architectures. • Edge-Based AI Execution – Enables on-device inference for improved data privacy and technological sovereignty. • Cost-Effective AI Acceleration – Optimized architecture targeting an attractive computational performance-to-cost ratio.
Key Features
- • High-Performance Matrix-Matrix Acceleration (MxM) – Dedicated hardware acceleration for compute-intensive neural network operations. • Monolithic Streaming Architecture – Optimized dataflow processing for efficient, high-throughput AI inference. • Scalable Processing Architecture – Configurable processing arrays, starting at 8 × 8 (64 processing elements), scalable to 32 × 32, 32 × 64, 64 × 64 and larger configurations. • Ultra-Low-Power AI Processing – Designed for energy-efficient Edge AI and TinyML applications. • High Computational Throughput – Parallel matrix processing to accelerate demanding AI workloads. • Efficient Data Streaming – Minimizes unnecessary data transfers to improve processing efficiency. • Low-Latency AI Inference – Supports fast, real-time neural network execution. • Configurable Hardware Architecture – Adaptable processing capacity to meet application-specific performance requirements. • Optimized Silicon Utilization – Designed to balance processing performance, power consumption and silicon area. • Continuous AI Processing – Supports always-on embedded intelligence. • Neural Network Acceleration – Suitable for convolutional neural networks (CNNs) and other matrix-intensive AI workloads. • Flexible SoC Integration – Designed for incorporation into embedded processors and semiconductor SoC architectures. • Edge-Based AI Execution – Enables on-device inference for improved data privacy and technological sovereignty. • Cost-Effective AI Acceleration – Optimized architecture targeting an attractive computational performance-to-cost ratio.
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 GX FPGA, Stratix® 10 MX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA |
|---|---|
| Offering Status | Production |
| Demo | Yes |
| Design Examples Available | Yes |
| Latest Quartus Version Supported | 25.1.2 |
| OS Support | INTERA’s Falcon Cognit is an IP core (not a standalone board with its own OS), host/development machine and the target/embedded environment. |
| Development Language | C/C++, Encrypted Verilog, Encrypted VHDL, Verilog, VHDL |
INTERA's Harrier Cognit is an Edge AI Accelerator IP core from INTERA Group, designed primarily for low-power, battery-powered inference at the edge. What is Included / Key Components 1. Core Product: Harrier Cognit AI Acceleration IP • AI acceleration Intellectual Property (IP) core. • Optimized for ultra-low power (ULP) inference. • Supports common neural network types: FC, DNN, MLP, CNN, and LSTM. • Integrates into FPGA, ASIC, and SoC designs. 2. Hardware Support • Available on FPGA Dev Boards and INTERA Dev Boards. • Can be used as a daughter board or integrated into custom SoC. 3. Software Suite (Comprehensive & Open-Source) • SDK (Software Development Kit) / Starter Development Kit. • Seamless interoperability with popular deep learning frameworks (Keras, TensorFlow, etc.). • Model Build Environment + Automated Profiling. • Runtime Environment + Firmware. • Demo applications and user guides. • Support for custom and user-provided models. 4. Key Features & Benefits • Battery-powered / Always-ON operation. • High power efficiency for edge devices. • Low latency real-time performance. • Data privacy (runs offline, no cloud needed). • Cost optimization (avoids cloud subscriptions). • Targeted at verticals like medical cognitive monitoring, healthcare, industrial IoT, energy, defense, etc. Offering Packages INTERA typically provides a Development Kit that includes: • The Falcon IP core • Sample models and applications • Development board(s) • Documentation (apps notes, user guide) • Tool suite / SDK
Ordering Information
HARRIER FPGA 003
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