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Altera High Level Synthesis IP Gen Compiler (Beta)

Overview

The HLS IP Gen compiler is a high-level synthesis tool that converts untimed C++-based SYCL code into optimized, production-quality RTL for Altera® FPGAs. By raising the abstraction level of design input, the HLS Compiler accelerates development and verification cycles compared to traditional RTL design flows. C++ models can typically be verified orders of magnitude faster, enabling more efficient iteration and system-level exploration.
HLS IP Gen replaces the SYCL FPGA toolchain previously distributed as the Intel oneAPI FPGA add-on. The tool now targets FPGA device families while also providing a fast path for software emulation. The Open FPGA Stack can be optionally used in user owned custom full stack to integrate the generated IP from HLS IP Gen. 

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Features

SYCL-based Compiler

Compile C++ and SYCL code for FPGAs, enabling code reuse and efficient parallel programming.

 

  • CPU emulator: Run your kernels on CPU to check functional correctness before synthesis.
Architecture Exploration

Quickly explore multiple architectures through high-level directives.

 

  • Pipes: FIFOs between kernels declared in source; compiler sizes the buffer above your minimum.
  • task_sequence: Launch tasks asynchronously and collect results later; each instance is its own hardware block.
  • Datapath cluster controls: Choose higher fMAX or lower area and latency per kernel; compiler picks the default.
Customizable FPGA Kernels

Optimize FPGA kernels with attributes, pragmas, and extensions to fine-tune performance and resource utilization.

 

  • Memory interfaces: Configurable load-store units for bursting, caching, and arbitration; multiple kernels can share a memory port.
IP Generation via Platform Designer

Generate reusable IP for system integration using Platform Designer.

 

  • Standard kernel interfaces: Avalon® Streaming, Avalon® Memory-Mapped and AXI-Stream; drop the generated IP into Platform Designer.
  • Generated RTL: Simulatable in Questa-Intel FPGA Edition or other supported Siemens Questa variants.
Timing-Driven Scheduling and Mapping

Performs device-specific timing-driven schedule optimization and technology mapping for Altera® FPGAs.

Design Utilization Insights

View and analyze area utilization, loop structure, memory usage, system data flow, clusters, and surrounding logic.

 

  • Optimization reports: System Viewer shows clusters, FIFOs, schedule, and dependencies traceable back to source.

Getting Started

 

  1. Download HLS IP Gen compiler 
  2. Refer to the Altera HLS Handbook and Release Notes for more details.
     
See the Getting Started Guide