Platform Designer

Overview

The Platform Designer is the next-generation system integration tool in the Altera Quartus Prime Software. The Platform Designer saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. The Platform Designer utilizes a powerful hierarchical framework to offer fast response times for interconnecting large systems, while also providing support for blackbox entities. This enables the Platform Designer to provide fast response times while opening systems and creating new connections by regenerating or operating on IP blocks that have changed. The new Platform Designer tool also supports a variety of design entry methods, such as register transfer level (RTL) languages, block-based design entry, to schematic entry, and black boxes.

Streamline FPGA System Integration with Platform Designer

Accelerate your development with automated system interconnects, IP reuse, and faster integration—directly inside Quartus® Prime.

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Key Features

Packaged Subsystem
  • Ability to easily package all or part of a Platform Designer system into an IP (component).
  • The resulting IP can then be found in the IP catalog.
  • Easily share and reuse in different projects inside or outside Platform Designer.
Board awareness
  • Faster design creation for Intel and 3rd party boards.
  • Ability to apply IP presets with pre-assigned pin locations and IO standards for a target board.
Faster development
  • Easy-to-use GUI interface enables quick integration between IP functions and subsystems.
  • Automatic generation of interconnect logic. (address/data bus connections, bus width matching logic, address decoder logic, arbitration logic, etc.)
  • Availability of plug-and-play Platform Designer-compliant IP. (Note: Platform Designer-Pro compliance is not available for all IP)
  • Support mixing of different industry-standard interfaces including Avalon®, Arm AMBA AXI, AMBA APB, and AMBA AHB interfaces.
  • Automatic HDL generation of your system.
  • Hierarchical design flow enables scalable designs, team-based design, and maximizes design reuse.
  • Migration flow to Platform Designer (does not apply to Platform Designer Pro) for SOPC Builder designs.
Faster timing closure
  • High-performance Platform Designer (Standard) interconnect based on the NoC architecture and automatic pipelining delivers higher performance compared to SOPC Builder’s system interconnect fabric .
  • Ability to control the aggressiveness of automatic pipelining to meet fMAX and latency system requirements.
Faster verification
  • Ability to start your simulation faster with automatic testbench generation and by using the verification IP suite.
  • Faster board bring-up with System Console by sending read-and-write transactions into a live system.