Visual Designer Studio (Beta)

Overview

Making Design Entry More Intuitive

The Visual Designer Studio is the next-generation system integration tool built to simplify and accelerate FPGA designs. It provides a highly visual and intuitive environment that enables quick automation and connection of IP blocks, data flow visualization, and improving productivity. 

Benefits

Connectivity
  • AXI-based IP interfaces & bridges
  • Smart connectivity and connection automation 
Intuitive Views
  • Full Integration with Quartus & consolidated IP catalog
  • GUI/Block-based Design Entry with drag and drop capabilities
  • Improved global address map view & editing 
IP-Centric Development
  • Seamless RTL import and system generation with templates for Verilog, VHDL and SystemVerilog
  • New streamlined TCL API and enhanced TCL commands for system creation and canvas action capture
  • Exportable TCL flow for fast system recreation and automation