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Stratix® 10 GX
High-performance FPGAs with leading transceiver bandwidth and HyperFlex® architecture for the most demanding applications.
Explore the Stratix® 10 GX FPGA
Stratix 10 GX FPGAs contain up to 10.2 million logic elements and feature 96 general-purpose transceivers across separate chiplets. With 2,666 Mbps DDR4 external memory interface performance, these devices are optimized for FPGA applications requiring maximum transceiver throughput, I/O bandwidth, and core fabric performance.
Key Features
| Hyperflex® FPGA Architecture | The core architecture delivers many advantages: higher throughput, improved power efficiency, greater design functionality, increased designer productivity and incorporates bypass-able hyper-registers. |
| Heterogeneous 3D System-in-Package (SiP) Transceiver Tiles | The transceivers are on the heterogeneous 3D SiP transceiver tiles, each containing 24 full-duplex transceiver channels offering solutions for connectivity needs and future flexibility and scalability needs as data rates, modulation schemes, and protocol IPs evolve. |
| Secure Device Manager (SDM) | SDM controls key operations, such as configuration, device security, single event upset (SEU) responses, and power management. It creates a unified, secure management system for the entire device, including the FPGA fabric, hard processor system (HPS) in SoCs, embedded hard IP blocks, and I/O blocks. |
Benefits
High Clock Performance and Lower Power Consumption
Stratix 10 FPGAs and SoC FPGAs use the Hyperflex core architecture, delivering higher throughput, improved power efficiency, enhanced design functionality, and increased developer productivity over previous-generation devices.
Runs on the Hyperflex FPGA Architecture
The Hyperflex FPGA Architecture introduces bypass-able Hyper-Registers throughout the FPGA fabric – on interconnect routing segments and at the inputs of all functional blocks. These Hyper-Registers enable three advanced techniques to optimize core performance: Hyper-Retiming reduces critical path delays; Hyper-Pipelining improves timing closure by minimizing routing congestion; and Hyper-Optimization enhances overall device performance by enabling more aggressive timing and resource utilization strategies.
Enabling Next-Generation Chiplets Using 3D System-in-Package Technology
The patented Embedded Multi-Die Interconnect Bridge (EMIB) technology provides high-density interconnect between heterogeneous dies in the same package. It enables in-package functionality that was previously too complex or cost-prohibitive to implement using traditional multi-die packaging methods.
Product Package & Combination Selector
Start Design
Everything you need to begin a Stratix 10 GX FPGA design.
Stratix 10 GX FPGA Signal Integrity Development Kit (L-TILE)
Features the Stratix 10 GX L-Tile FPGA (1SG280LU2F50E2VG) with transceiver performance up to 17.4 Gbps (L-Tile)
Stratix 10 GX FPGA Signal Integrity Development Kit (H-TILE)
Features the Stratix 10 GX H-Tile FPGA (1SG280HU1F50E2VG) with transceiver performance up to 28.3 Gbps (H-Tile)
Find Partner Boards
Stratix 10 FPGA H-Tile Hard IP for Ethernet
This IP core configures the transceivers to implement the relevant specification for your IP core variation.
10GBASE-R PHY FPGA IP
This IP core allows connectivity directly with any XFP or SFP+ optical module or with any external device with XFI and SFI interfaces.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
Jumpstart your project with the latest design examples targeting Quartus® Prime Design Software v16.0 and above.
Solutions
Stratix 10 GX FPGAs for Wireline
Stratix 10 GX FPGAs for Test and Measurement
Stratix 10 GX FPGAs for Broadcast and Pro AV
Resources
Start developing with Stratix 10 GX FPGAs with these resources.
Training & Learning
Common Questions
Match required rate and protocol support to the tile and device. The page's example kits have different supported transceiver rates.
Use suitable pipelining, manageable fanout and accurate constraints, then inspect critical paths and physical placement in the Quartus Prime Pro Edition software.
Family maxima refer to specific parts. Select the actual device from its resource table before budgeting logic, memory and channels.
Calculate aggregate reads, writes and reuse, then include arbitration and memory efficiency. Keep compute lanes balanced with available data supply.
Check unconstrained timing, unsafe clock crossings and reset assumptions. Placement-sensitive symptoms can expose marginal or incorrectly constrained logic.