Products

Altera® offers a complete range of FPGAs, SoCs, and CPLDs spanning high-performance, mid-range, and power and cost-optimized families so you can match the right device to your performance, power, and budget targets.

Mid Range

Altera mid-range FPGAs balance performance, power efficiency, and integration for industrial, embedded, communications, and edge designs, with the field programmability to adapt as requirements change.

Development Kits

Accelerate FPGA development with Altera kits featuring tabletop and PCIe platforms, high-speed interfaces, HPS enablement, and full device family.

High Performance

Mid Range

Power & Cost Optimized

Agilex 3

Cyclone 10

Cyclone IV

MAX V

Software & Tools

A complete suite of development tools for every stage of your Altera FPGA, SoC, or CPLD design. Whether you're building hardware, writing embedded software, modeling DSP algorithms, or architecting full systems, the right tool is ready to accelerate your workflow.

AI Development Tools

FPGA Al Suite

Build and deploy hardware-accelerated inference on your FPGA

FPGA Design & Simulation Tools

Quartus Prime Design Software

Compile, place-and-route, and program your design

Power and Thermal Analyzer

Estimate device power and thermal early

Questa* - Altera FPGA Edition

Simulate and verify your RTL before hardware

Advanced Link Analyzer

Model and tune high-speed serial links

Open FPGA Stack (OFS)

Build custom acceleration platforms on an open foundation

Transceiver Toolkit

Characterize and debug transceiver links on hardware

Embedded Design Tools & Software

Nios® V

Add a soft Nios-V processor to your FPGA design

Ashling* RISCFree IDE

Develop and debug software for Nios V and RISC-V

Visual Designer Studio

Build FPGA applications with a graphical, model-based flow

Intel® Simics® Simulator for Altera® FPGAs

Develop firmware before hardware is ready

Arm* Development Studio for Altera SoC FPGAs

Program and debug the Arm cores in Altera SoC FPGAs

IP Development Tools

DSP Builder

Generate optimized DSP datapaths from MATLAB/Simulink

HLS IP Gen (Beta)

Accelerate FPGA development by transforming high-level C++ and SYCL designs into optimized, production-quality RTL.

P4 Suite for PFGAs

Write the data plane in P4. Get synthesizable RTL and a runtime API for Altera® FPGAs, without hand-coding the hardware.

Intellectual Property

Build faster with Altera’s broad IP portfolio combining soft and hardened IP cores, reference designs, and partner solutions for a wide variety of FPGA applications.