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The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration. This IP allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G. It handles the frame encapsulation and flow of data between a client logic and Ethernet network via PCS and PMA (PHY).
Altera
Key Features
- Implements the Ethernet protocol as defined in clause 36 of the IEEE 802.3 2005 standard
- Consists of a physical coding sublayer (PCS) function and an embedded physical medium attachment (PMA)
- Dynamically switchable PHY operating speed; 1G/2.5G, 2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G (MGBASE-T), 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M, 100M, 1G, 2.5G, and 10G (MGBASE-T) operating modes
- Users needing Copper-PHY capability for USXGMII, MGBASE-T modes will need to use an external PHY chip
- Avalon® memory-mapped interface for PHY management
- Datapath client interface: 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
- Datapath Ethernet interface: 10M/100M/1G/2.5G/5G/10G (USXGMII)—Single 10.3125 Gbps serial link
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 TX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Development Language | Encrypted Verilog |
Encrypted Verilog source code
Design Example
Simulation Models
IP Evaluation Mode
Documentation: IP User Guide, Design Example User Guide, IP Release Notes
Ordering Information
IP-10GMRPHY
from Digikey
IP-10GMRPHY
from Mouser
Documentation & Resources
Market Segment and Sub-Segments
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Aerospace
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ASIC Proto
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