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Low Latency Ethernet 10G MAC FPGA IP

Altera

The Low Latency Ethernet 10G MAC FPGA IP core offers low round-trip latency and efficient resource footprint. This IP core offers programmability of various features listed. It can be used in conjunction with the Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

Key Features

  • Full-duplex MAC in one or eight operating modes depending on the supported device
  • MAC TX only, MAC RX only, or both MAC RX and TX operating modes depending on device; Programmable promiscuous (transparent) mode
  • Client: 32-bit Avalon streaming interface (Avalon-ST); Management: 32-bit Avalon-MM interface
  • Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath
  • Optional CRC checking and forwarding on the RX datapath
  • Optional timestamping (specified in IEEE 1588v2)
  • Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications
  • Programmable IPG

Offering Brief

Offering Brief

Device Family Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV GX FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GX FPGA
Offering Status Production
Evaluation License Yes
Design Examples Available Yes
Demo Yes
Development Language Encrypted Verilog

Encrypted Verilog source code

Design Example

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, Design Example User Guide, IP Release Notes

Ordering Information

Market Segment and Sub-Segments