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The 25G Ethernet IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The media access control (MAC) client side interface for the 25GE IP core is a 64-bit Avalon streaming interface (Avalon-ST). It maps to one 25.78125 Gbps transceiver. The IP core optionally includes Reed-Solomon Forward Error Correction (FEC) for support of direct attach copper (DAC) cable. The 25G Ethernet Altera FPGA IP core with various optional features is also available as hard IP on Stratix 10 devices with E-Tiles. More details can be found on the E-Tile Hard IP for Ethernet page.
Altera
Key Features
- Soft PCS logic that interfaces seamlessly to Stratix 10 FPGA 25.78125 gigabits per second (Gbps) or 10.3125 Gbps serial transceivers
- Support for dynamic reconfiguration between the Ethernet data rates of 25.78125 Gbps and 10.3125 Gbps
- Support for jumbo packets, defined as packets greater than 1500 bytes
- Receive (RX) CRC removal and pass-through control
- Transmit (TX) CRC generation and insertion; RX CRC checking and error reporting
- Standard IEEE 802.3 Clause 31 and Priority-Based IEEE 802.1Qbb flow control
- Optional support for the IEEE Standard 1588-2008 Precision Clock Synchronization Protocol (1588 PTP)
- TX error insertion capability
- Avalon Streaming (Avalon-ST) data path interface connects to client logic
- Optional Reed-Solomon forward error correction (FEC)
- Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers
Offering Brief
Offering Brief
| Device Family | Arria® 10 GT FPGA, Stratix® 10 GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Development Language | Encrypted Verilog |
Encrypted Verilog source code
Design Example
Simulation Models
IP Evaluation Mode
Documentation: IP User Guide, Design Example User Guide, IP Release Notes
Ordering Information
IP-25GEUMACPHY; IP-25GEUMACPHYF; IP-25GEUMACPHYFC; IP-25GEUMACPHYFFC
from Digikey
IP-25GEUMACPHY; IP-25GEUMACPHYF; IP-25GEUMACPHYFC; IP-25GEUMACPHYFFC
from Mouser
IP-25GEUMACPHY; IP-25GEUMACPHYF; IP-25GEUMACPHYFC; IP-25GEUMACPHYFFC
from Digikey
IP-25GEUMACPHY; IP-25GEUMACPHYF; IP-25GEUMACPHYFC; IP-25GEUMACPHYFFC
from Mouser
IP-25GEUMACPHY; IP-25GEUMACPHYF; IP-25GEUMACPHYFC; IP-25GEUMACPHYFFC
from Digikey
IP-25GEUMACPHY; IP-25GEUMACPHYF; IP-25GEUMACPHYFC; IP-25GEUMACPHYFFC
from Mouser
IP-25GEUMACPHY; IP-25GEUMACPHYF; IP-25GEUMACPHYFC; IP-25GEUMACPHYFFC
from Digikey
IP-25GEUMACPHY; IP-25GEUMACPHYF; IP-25GEUMACPHYFC; IP-25GEUMACPHYFFC
from Mouser
Documentation & Resources
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