MACsec FPGA IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The MACsec FPGA IP core is a fully configurable soft IP that implements the IEEE Media Access Control Security standard as defined in 802.1AE (2018). MACsec provides data confidentiality and integrity for the Ethernet protocol and is commonly used to secure network traffic in a variety of different applications.

This IP core makes use of the Symmetric Cryptographic Accelerator (SCA) Hard IP, which is available in select Agilex 7 F-series and I-series devices. With the SCA, Altera's MACsec IP core can achieve 100 Gbps full-duplex line rates. Note that the SCA can also be used as a stand alone cryptographic accelerator.

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Key Features

Altera developed, fully featured soft IP core
Support for cipher suites (GCM-AES-128/256, GCM-AES-XPN-128/256)
Supports SecTAG and ICV insertion/removal, and VLAN Tag
Configurable store-and-forward versus cut through mode for each stream
Support for stream interleaving on user and AES interfaces
Supports controlled and uncontrolled ports with configurable data widths
Supports 2 Tx and 2 Rx security channels (SC) per port
Security association shall be 4 per SC, total of up to 1024 SA for 64 ports
Integration with the 200Gbps AES and SM4 Inline Crypto Accelerator hard IP, or user provided soft AES IP
User packet bypass metadata to support PTP use cases
Optional RX Replay Protection Check based on Replay Window, Lowest Acceptable PN, Next PN
64 bits MACSEC Statistic Counters per MACSEC specification on each SC and SA

Offering Brief

Device Family	Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Verilog, VHDL