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L/H-Tile are each an FPGA companion tile in Stratix® 10 FPGA devices that support configurations up to PCIe 3.0 x16 in Endpoint (EP) and Root Port (RP) modes. Additionally, H-Tile includes support for SR-IOV functionality.
Altera
Key Features
- Complete PCIe Protocol Stack in Hard IP – Full implementation of Transaction, Data Link, and Physical Layers with up to PCIe 3.0 lane rates.
- Flexible User Interfaces – Avalon® Streaming and Avalon® Memory-Mapped.
- Multiple Mode Options – Root Port, Endpoint, and SR-IOV (4 PFs, 2K VFs - H-Tile only).
- Seamless Integration Options – Instantiable from Quartus® Prime Pro Edition IP Catalog or as part of a Platform Designer system, with dynamic design example generation.
- SR-IOV Features – AER, ATS, TPH, Control Shadow Interface for VF Control Register Fields, FLR and MSI-X for PFs/VFs, and MSI for VFs.
- Configuration & PHY Simulation Support – Supports CVP Init/Update, PIPE or serial PHY interface simulation, and Avery BFM support for PCIe 3.0 x16 simulation.
- Clocking Integration – Supports multiple clocking modes (Reference Clock (refclk) with SRNS, but not SRIS).
- Enhanced Reliability & Debug – Advanced Error Reporting for PFs, PCIe Link Inspector toolkit: LTSSM monitoring, read/write access to PCIe Configuration Space Registers, and PCS and PMA registers.
- Complementary IP Ecosystem – Seamless integration with Avalon® Memory-Mapped (AVMM) and Multichannel DMA IP.
- Comprehensive Software Support – Ready-to-use Linux device drivers, plus Windows device drivers via Jungo partner for faster deployment.
Offering Brief
Offering Brief
| Device Family | Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Compliance | Yes |
| Compliance Link | Compliance Link |
| Development Language | Encrypted Verilog |
Encrypted Verilog Source Code
Design Example(s)
Simulation Models
IP Evaluation Mode
Documentation: IP User Guides, Design Example User Guides, IP Release Notes
Ordering Information
No license required
from Delivered with Quartus
Documentation & Resources
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