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Arria® 10 and Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with the PCI Express Base Specification 3.0 and PCI Express Base Specification 2.0 respectively. The hard IP provides the Avalon® Streaming (Avalon-ST) interface and can be configured for either Root Port (RP) or Endpoint (EP) modes. Complementary soft IPs are available for Single Root I/O Virtualization (SR-IOV) support and bridging to an Avalon Memory-Mapped interface (Avalon-MM) with DMA functionality.
Altera
Key Features
- Complete PCIe Protocol Stack in Hard IP – Full implementation of Transaction, Data Link, and Physical Layers with PIPE mode support.
- Broad PCIe Version Support – Arria 10 : PCIe 3.0/2.0/1.1 (x8/x4/x2/x1) and Cyclone 10: PCIe 2.0/1.1 (x4/x2/x1).
- Flexible Port & Mode Options – Root Port, Endpoint, and SR-IOV (8 PFs, 2K VFs) support.
- Versatile User Interfaces – Avalon-ST, Avalon-MM, and Avalon-MM DMA for design flexibility.
- High Performance Data Handling – Up to 2048B (Avalon-ST) and 256B (Avalon-MM) Maximum Payload Size (MPS) and 8-bit tag support for outstanding transactions.
- Configuration & Partial Reconfiguration Over PCIe – Supports CVP Init and Partial Reconfiguration (PR) over PCIe link.
- Complementary IP Ecosystem – Seamless integration with PCIe SR-IOV (Avalon-ST interface) and DMA IP (Avalon-MM interface).
- Comprehensive Software Support – Ready-to-use Linux device drivers, plus Windows device drivers via Jungo partner for faster deployment.
Offering Brief
Offering Brief
| Device Family | Arria® 10 GX FPGA, Cyclone® 10 GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Compliance | Yes |
| Compliance Link | Compliance Link |
| Development Language | Encrypted Verilog |
Encrypted Verilog Source Code
Design Example(s)
Simulation Models
IP Evaluation Mode
Documentation: IP User Guides, Design Example User Guides, IP Release Notes
Ordering Information
No license required
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Documentation & Resources
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