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R-Tile is a FPGA companion tile in Agilex® 7 FPGA I-Series and M-Series devices that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass modes. PCIe 3.0, 4.0, and 5.0 configurations are natively supported. R-Tile also supports up to 16 SerDes channels through a PHY Interface for PCIe (PIPE) 5.1.1 in SerDes Architecture mode.
Altera
Key Features
- Complete PCIe Protocol Stack in Hard IP – Full implementation of Transaction, Data Link, and Physical Layers with PIPE mode support.
- Broad PCIe Version Support – Native PCIe 5.0/4.0/3.0 with seamless down-training to 2.0/1.0.
- Flexible Port & Mode Options – Root Port, Endpoint, TL-Bypass, SR-IOV (8 PFs, 2K VFs), and bifurcation support.
- High Performance Data Handling – Up to 512B Maximum Payload Size (MPS), 4KB Maximum Read Request Size (MRRS), and extended 10-bit tag support for hundreds of outstanding transactions.
- Versatile User Interfaces – Avalon-ST, AVMM, segmented packet interfaces, and support for simultaneous TLP handling.
- Configuration & Partial Reconfiguration Over PCIe – Supports CVP Init / Update and Partial Reconfiguration (PR) over PCIe link.
- Robust System Integration – Supports multiple clocking modes (Common/Independent Reference Clock (refclk) with and without Spread Spectrum SRIS, SRNS), Precision Time Management (PTM), and power states (D0/D3).
- Enhanced Reliability & Debug – Advanced Error Reporting, Debug toolkit: detailed protocol/link status, PMA register access, and eye viewing capability.
- Complementary IP Ecosystem – Seamless integration with PCIe Scalable Switch IP and DMA IPs (AXI and Avalon interfaces).
- Comprehensive Software Support – Ready-to-use Linux device drivers for faster deployment.
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Compliance | Yes |
| Compliance Link | Compliance Link |
| Development Language | Encrypted Verilog |
Encrypted Verilog Source Code
Design Example(s)
Simulation Models
IP Evaluation Mode
Documentation: IP User Guide, Design Example User Guide, IP Release Notes
Ordering Information
No license required
from Delivered with Quartus
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