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FPGA Software and Tools
FPGA AI Suite
Bring pretrained models into FPGA designs with FPGA AI Suite and OpenVINO. Validate model accuracy, optimize resources, and integrate low-latency AI into your design.
FPGAs Play a Vital Role in Enabling Efficient AI Infrastructure
- FPGAs provide deterministic, low-latency sensor capture, pre-processing, and data movement for Edge AI and Physical AI systems, while a GPU or other compute runs the model.
- FPGA-based SmartNICs and DPUs assist CPUs, GPUs, and ASICs for AI training and inferencing workloads by offloading data connectivity, data preprocessing, and sensor fusion tasks, resulting in compute cores operating at higher efficiency.
Altera’s FPGA AI Suite software is a complete solution for creating AI accelerators on Altera FPGAs and SoCs, specifically for teams that want to move quickly, whether you're coming from a software background, an FPGA background, or both. Instead of requiring deep FPGA expertise at every step, the development flow focuses on making model conversion, optimization, and integration easier.
- Data scientists focus on building and validating models.
- FPGA engineers integrate accelerator IP and meeting system constraints like timing and resources.
- Software integrators connect everything to the host side.
Coordinating these roles can slow projects down when changes are frequent. FPGA AI Suite helps reduce that friction by providing common artifacts and well-defined handoffs between teams.
1. Model
Data scientists work on training the Deep Learning model best suited for the application, using existing AI frameworks (PyTorch, ONNX, etc.).
2. Convert
The open-source OpenVINO™ toolkit converts pretrained models to an intermediate representation (IR files, .xml, .bin).
3. Generate
FPGA AI Suite takes the IR files and creates an estimated area and performance, or generates an optimized architecture, then compiles network files into a .bin to run on the host (FPGA and/or CPU). Inference Runtime: The .bin file is loaded by your application at runtime via Inference Engine and FPGA AI APIs for memory and hardware scheduling. Emulation: Evaluate the FPGA AI IP accuracy using the OpenVINO plugin. Sample designs show how to run inference on the host (x86, Arm, RISC-V, or hostless).
4. Deploy
FPGA AI Suite creates a complete AI functional block that is easily incorporated into the rest of the FPGA design, using Altera’s Quartus Prime software and other software tools (Platform Designer, DSP Builder, etc.). FPGA hardware testing: Once the full FPGA design is complete, Quartus software creates a programming file that is downloaded into the target Altera FPGA hardware.
What's New
New Features that Advance Edge AI Inference
Key Highlights:
Public release (beta) of the new spatial compiler, a new architectural option with MLP support that maps a network's dataflow directly into FPGA fabric, eliminating the instruction-fetch and weight-streaming overhead characteristic of sequential accelerators.
- Architecture Optimizer Enhancements
- Bit-Accurate Emulation and Simulation got Faster
Spatial Architecture Boosts Edge AI Inference on Altera FPGAs
The new Spatial Compiler generates dedicated RTL, slashing latency by 28x with 80% fewer resources for real-time Physical AI.
Benefits
Push-Button Optimized AI IP Generation
FPGA AI Suite seamlessly generates optimal AI inference IP from pre-trained AI model sweeping the design space for optimal resources to performance targets.
Hardware-less Early Model Validation
Bit-accurate software emulation of the AI inference IP is available through the OpenVINO plugin interface, enabling quick evaluation of the accuracy of the model without hardware.
Simple and Standard Flows
Create and add AI inference IP to current or new FPGA designs with Quartus Prime Software and other software tools.
Get Started
FPGA AI Suite Documentation
Get user guides, release notes, and more.
Resources
Demo Videos
Spatial Architecture
Learn how spatial architecture enables FPGAs to deliver high-performance, energy-efficient computing by executing many operations in parallel rather than sequentially. This video explains how customizable hardware pipelines and parallel processing help accelerate AI, signal processing, networking, and other compute-intensive workloads while reducing latency and improving throughput.
Overview of Altera’s FPGA AI Suite Software
Altera’s FPGA AI Suite software is a complete solution for creating AI accelerators on Altera FPGAs and SoCs, specifically for teams that want to move quickly, whether you're a data scientist, SoC embedded software designer, or an FPGA designer.
FPGA AI Suite Docker Install
This video walks through setting up the FPGA AI Suite using docker to get everything ready for development.
Common Questions
Choose FPGA AI Suite for supported model-to-accelerator flows. Choose custom HLS when an algorithm needs bespoke processing outside that supported flow.
Check the compiler's operator support and partitioning options. Revise unsupported layers or use documented host execution where the selected flow supports it.
It reproduces accelerator arithmetic in software, letting you compare outputs with the reference model before programming hardware.
Evaluate spatial compilation for supported models requiring dedicated dataflow hardware. Check beta limitations and compare measured latency, area and accuracy.
Measure system-level latency and throughput with representative inputs, including memory transfers, preprocessing and host overhead. Peak arithmetic capacity alone is insufficient.
Ready to Order?
Ordering starts with a part number. Select a product in the table above to view its ordering part numbers (OPNs) — which encode density, speed grade, package, and options — then use that OPN to check availability and purchase through an authorized distributor. Refer to Parts Decoder to decode a OPN.