Software and Tools

Altera High Level Synthesis IP Gen Compiler (Beta)

Q: How does a developer migrate an FPGA oneAPI kernel to HLS IP Gen?

Review the migration guidance, update the build flow, regenerate kernel IP, and integrate it into the target FPGA system.

Q: How does a high initiation interval limit an HLS-generated FPGA kernel?

A larger initiation interval reduces the rate at which new work enters the pipeline. Inspect dependencies and memory access constraints in optimization reports.

Q: How does a designer avoid deadlock between SYCL pipe-connected kernels?

Analyze producer-consumer rates and blocking dependencies. Choose suitable FIFO depth and verify that every required read and write can progress.

Q: When should an HLS kernel use streaming rather than memory-mapped interfaces?

Use streaming for continuous data pipelines and memory-mapped access for addressable storage or control. Match the interface to system traffic patterns.

Accelerate FPGA development by transforming high-level C++ and SYCL designs into optimized, production-quality RTL.

Download HLS IP Gen (Beta)

Overview

The HLS IP Gen compiler is a high-level synthesis tool that converts untimed C++-based SYCL code into optimized, production-quality RTL for Altera® FPGAs. By raising the abstraction level of design input, the HLS Compiler accelerates development and verification cycles compared to traditional RTL design flows. C++ models can typically be verified orders of magnitude faster, enabling more efficient iteration and system-level exploration.

HLS IP Gen replaces the SYCL FPGA toolchain previously distributed as the Intel oneAPI FPGA add-on. The tool now targets FPGA device families while also providing a fast path for software emulation. The Open FPGA Stack can be optionally used in user owned custom full stack to integrate the generated IP from HLS IP Gen.

Key Features

SYCL-based Compiler	Compile C++ and SYCL code for FPGAs, enabling code reuse and efficient parallel programming. CPU emulator: Run your kernels on CPU to check functional correctness before synthesis.
Architecture Exploration	Quickly explore multiple architectures through high-level directives. Pipes: FIFOs between kernels declared in source; compiler sizes the buffer above your minimum. task_sequence: Launch tasks asynchronously and collect results later; each instance is its own hardware block. Datapath cluster controls: Choose higher f_MAX or lower area and latency per kernel; compiler picks the default.
Customizable FPGA Kernels	Optimize FPGA kernels with attributes, pragmas, and extensions to fine-tune performance and resource utilization. Memory interfaces: Configurable load-store units for bursting, caching, and arbitration; multiple kernels can share a memory port.
IP Generation via Platform Designer	Generate reusable IP for system integration using Platform Designer. Standard kernel interfaces: Avalon® Streaming, Avalon® Memory-Mapped and AXI-Stream; drop the generated IP into Platform Designer. Generated RTL: Simulatable in Questa-Intel FPGA Edition or other supported Siemens Questa variants.
Timing-Driven Scheduling and Mapping	Performs device-specific timing-driven schedule optimization and technology mapping for Altera FPGAs.
Design Utilization Insights	View and analyze area utilization, loop structure, memory usage, system data flow, clusters, and surrounding logic. Optimization reports: System Viewer shows clusters, FIFOs, schedule, and dependencies traceable back to source.