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Software and Tools
Advanced Link Analyzer
Model FPGA serial-link signal integrity with Advanced Link Analyzer. Evaluate jitter, eye diagrams, NRZ and PAM4 links before committing to a PCB design.
Overview
The Advanced Link Analyzer is a state-of-the-art jitter/noise eye link analysis tool that allows you to quickly and easily evaluate high-speed serial link performance. It is an ideal pre-design tool supporting FPGA IBIS-AMI standard and enhanced models to help you understand how FPGA solutions can fit your system requirements. It is also an effective tool for post-design support to assist in debug and validation, providing silicon correlated end-to-end simulation over various Process Variation and Temperature (PVT).
Benefits
Reduces Time to Design Success
- Silicon and package characterization/correlation of integrated models
- Link simulation that comprehends PVT variations
- Hybrid simulation with statistical and time-domain analysis
- Support for NRZ and PAM4 modulation schemes
- Reference clock jitter and PLL subsystem analysis
Simplifies Link Analysis
Make complex link analysis easier with an integrated, streamlined simulation environment.
- Self-contained, holistic link analysis tool
- Push-button link analysis enabling simulation in minutes
- Support for industry-standard models, including IBIS-AMI 7.0 and Touchstone 2.0 S-Parameters
- Comprehensive performance analysis including eye diagrams, bathtub curves, jitter analysis, and waveforms
Enables Faster Link Optimization
Quickly evaluate, optimize, and validate channel performance.
- Fast, accurate, and comprehensive link optimization
- Channel compliance checks, including COM
- Channel characteristics analysis
- Comprehensive channel design environment for what-if analysis
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Common Questions
Use statistical analysis for rapid probabilistic eye assessment. Use time-domain analysis when waveform behavior or model limitations require transient evaluation.
Use channel files with correct port mapping, reference impedance and frequency coverage, then verify package and connector contributions.
Compare model assumptions with actual clocks, equalization, channel loss and operating conditions. Simulation accuracy depends on realistic inputs.
Supplement simulation with board BER testing during bring-up and qualification, especially across expected voltage, temperature and traffic conditions.