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Quartus Prime Design Software
Partial Reconfiguration
Swap out one region of your FPGA on the fly while the rest of the design keeps running, so multiple functions can time-share the same silicon without a bigger device.
Overview
Partial reconfiguration (PR) divides a design into a static region, which stays live, and one or more reconfigurable partitions that can be reprogrammed at run time. Each partition can hold several personas, alternative implementations that you load into the same region as the application demands, without disturbing logic outside it. The Quartus® Prime software flow supports PR on Agilex®, Stratix® 10, and Arria® 10 devices, with a push-button compile flow, hierarchical child partitions, simulation of the reconfiguration itself, and Signal Tap debug across both static and PR regions.
Key Features
The partial reconfiguration flow includes the following key features:
- Speed up in partial reconfiguration time for Stratix 10 devices
- Push-button PR flow for faster time to market
- Compliments existing script-based flow
- Command line and graphical user interface for compilation and analysis
- Hierarchical partial reconfiguration that allows you to create child PR partitions in your design
- Simulation of partial reconfiguration that allows you to observe the resulting change and the intermediate effect in a reconfiguration partition
- Signal Tap logic analyzer debug with simultaneous acquisition of both the static region and partial reconfiguration regions
Resources
Example Designs & Tutorials
Documentation
- Partial reconfiguration solutions IP user guide
- AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Agilex F-Series FPGA Development Board ›
- AN 987: Static Update Partial Reconfiguration Tutorial for Agilex F-Series FPGA Development Board ›
- AN 964: Signal Tap Tutorial for Agilex Partial Reconfiguration Design ›
- AN 954: Hierarchical Partial Reconfiguration Tutorial for Agilex F-Series FPGA Development Board ›
- AN 953: Partially Reconfiguring a Design on Agilex F-Series FPGA Development Board ›
- AN 826: Hierarchical Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board ›
- AN 825: Partially Reconfiguring a Design on Stratix 10 GX FPGA Development Board ›
- AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Stratix 10 Devices ›
- AN 819: Partial Reconfiguration over PCI Express Reference Design for Stratix 10 Devices ›
- AN 818: Static Update Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board ›
- AN 817: Static Update Partial Reconfiguration Tutorial for Arria 10 GX FPGA Development Board ›
- AN 813: Hierarchical Partial Reconfiguration over PCI Express Reference Design for Arria 10 Devices ›
- AN 806: Hierarchical Partial Reconfiguration Tutorial for Arria 10 GX FPGA Development Board ›
- AN 797: Partially Reconfiguring a Design on Arria 10 GX FPGA Development Board ›
- AN 784: Partial Reconfiguration over PCI Express Reference Design for Arria® 10 Devices ›
Online Training
Instructor-Led / Virtual Training
Common Questions
Quiesce traffic and isolate partition interfaces during reconfiguration, then restore clocks, resets and handshakes according to the documented flow.
Use PR when functions can share a region while essential static services continue. Assess partition overhead and switching time first.
Include bitstream transfer, configuration, initialization and traffic recovery. Use measured system timing rather than configuration bandwidth alone.
Build personas against the approved static interface and constraints. Validate compilation compatibility and simulate boundary behavior before hardware testing.
Detect the failure, keep interfaces isolated, and use a validated recovery image or system restart as required by the platform design.