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Development Software
Questa* – Altera® FPGA Edition
Verify Altera FPGA designs with Questa FPGA Edition. Simulate HDL testbenches, use device libraries, and debug waveforms before programming hardware.
Overview
Questa* – Altera® FPGA Edition makes it easier to move from ModelSim* FPGA Edition to a modern, flexible FPGA simulation and debug environment. Explore the migration video and Questa* – Altera FPGA Edition Quick-Start Guide to get started quickly, then discover enhanced debug capabilities through the demo—including causality traceback to identify the source of incorrect values, performance profiling, C debugging with VPI, DPI, and SystemC, and a customizable GUI with Tk. Together, these resources help teams transition smoothly, analyze designs more efficiently, and streamline FPGA verification.
Benefits
Questa* – Altera FPGA Edition Software
- Up to 2.5x/1.25 x faster Verilog/VHDL simulations compared to ModelSim*– FPGA Edition.
- Note: Performance measured by Siemens EDA. Performance is highly design-dependent and was measured by Siemens across 3 designs. Individual results may be higher or lower. No line limitations.
- Free with purchase of Quartus® Prime. Also available for separate purchase. Buy here.
- Note: Questa* – Altera FPGA Edition software license expires 12 months after the date of purchase. Every 12 months you must regenerate your license file in the Self-Service Licensing Center for the specific Questa*- Altera FPGA Edition software version that you purchased.
- Mixed language support – Verilog/SystemVerilog, VHDL and SystemC.
Questa* – Altera FPGA Starter Edition Software
- No line limitations.
- 40% performance (on average) of Questa* – Altera FPGA Edition Software.
- Log into Self Service Licensing Center to get free one-year license.
- Renew in SSLC annually, after one year. Click on Evaluation and Free Licenses tab in SSLC.
- Mixed language support – Verilog/SystemVerilog, VHDL and SystemC.
Key Features
| Mixed-Language Simulation | Run simulations across Verilog, SystemVerilog, and VHDL in a unified environment. |
| Precompiled Libraries | Use ready-to-go simulation libraries tailored for Altera devices—no setup needed. |
| NativeLink Integration with Quartus® Prime | Launch simulations directly from Quartus for a seamless verification flow. |
| Behavioral and Gate-Level Simulation | Validate functionality and timing accuracy at every stage of design. |
| HDL Testbench Support | Build and simulate testbenches to ensure robust functional coverage. |
| Waveform Debugging and GUI | Analyze signals with an intuitive GUI for faster debug and visualization. |
Common Questions
Use the correct device libraries and IP-generated simulation files, then verify compile order, library mapping and matching tool versions.
Inspect reset, initialization, undriven nets and competing drivers. Trace the earliest unknown value rather than only the final failing output.
Use behavioral simulation for fast functional verification. Use gate-level simulation for implementation-specific checks that the supported flow can model.
Generate a renewed license through the stated licensing service and configure the simulator to use that file.
Simulation tests exercised scenarios. Static timing analysis checks constrained timing paths that may not be sensitized by the testbench.