Technology Solution

Sensor Interfaces Holoscan Sensor Bridge

FPGAs are the data plane, pre-processing data from a variety of sensors into GPU memory over standard Ethernet.

NVIDIA Holoscan Sensor Bridge Solutions for AI Applications

Physical AI is driving an explosion of sensors (cameras, radar, lidar, others), creating a challenge of ingesting and synchronizing massive amounts of real-time data. Altera® FPGAs implement sensor aggregation, protocol conversion, timestamping, pre-processing, and early fusion before data reaches the GPU.

The Challenges, and Why FPGA

The Challenge

Many Protocols, One Ingest Path

Cameras, radar, IMUs, and other sensors arrive on their own interface. The AI compute expects one synchronized data pipeline for accurate decisions.

Why FPGA

Many Sensors, One Aggregation Point

One FPGA ingests, fuses, and timestamps a mixed set of sensor data into a low-latency, deterministic data stream for GPU processing.

The Challenge

CPU-Mediated Capture vs. Real-Time Inference

Routing sensor traffic through the host CPU adds copies, interrupts, and scheduling variability that real-time inference cannot absorb.

Why FPGA

Ultra-Low Latency by Construction

Capture, packetization, and preprocessing run as parallel hardware pipelines, not scheduled software tasks. The FPGA path is deterministic.

The Challenge

Fixed-Function Bridges vs. Evolving Sensors

Sensor technology turns over faster than design cycles. An ASIC’s I/O protocols chosen today may not satisfy tomorrow’s interfaces.

Why FPGA

Reprogrammable Interfaces, No Respin

Add or change a sensor interface through FPGA reconfiguration. The design is updated rather than a silicon respin, and no new PCB is needed.

Why Altera

Broadest Sensor Connectivity

Ingest MIPI, JESD204, HDMI, SDI, CAN, SPI, and more I/O interfaces, then send it to NVIDIA GPUs over one Ethernet interface.

Deterministic, Low-Latency Data Path

Agilex® FPGAs mix compute, memory, and I/O for packetization, preprocessing, and fusion, sending data to GPUs deterministically.

Edge to Data Center, One Architecture

Agilex devices offer solutions spanning 1G to 800G Ethernet, from NVIDIA Jetson to DGX-class systems on a single architecture.

Get Started

Best for Physical AI and Edge Deployment

Agilex 5 FPGAs and SoC FPGAs

FPGAs with integrated ARM-based SoC subsystem, ample logic and memory resources, validated to run Holoscan Sensor Bridge 10G and 25G reference designs on targeted boards.

Best for 100G – 400G High-Bandwidth Aggregation

Agilex 7 FPGAs and SoC FPGAs

FPGAs with the highest-performance compute fabric, memory, and I/O for aggregating the largest sensor populations at the top of the FPGA bandwidth range and validated on Holoscan targeted boards.

Best for Quantum Computing

Agilex 9 SoC FPGA Direct RF-Series

FPGAs with integrated converters (ADCs/DACs) that utilize NVQLink/Holoscan or QECi interfaces to implement precise qubit control, fast readout, or quantum error correction (QEC) algorithm acceleration.

Best For 1G to 10G SWaP Applications

Agilex 3 FPGAs and SoC FPGAs

Power- and cost-optimized FPGAs in small form-factor packages with best-in-class FPGA performance for compute, SoC subsystem, memory, and I/O resources for power- and weight-sensitive applications.

Best For 100G Streaming

Stratix® 10 FPGAs and SoC FPGAs

The ecosystem’s first validated 100G Holoscan FPGA-based solution (Stratix 10 TX variant). See Agilex 7 products for additional performance, power efficiency, and device features offered.

Common Questions

The FPGA packetizes sensor data in hardware and transports it over RoCE-based Ethernet directly into GPU memory using NVIDIA HoloLink IP and GPUDirect RDMA. Removing the host CPU from the data path eliminates the memory copies, interrupts, and scheduling variability that make software-mediated sensor ingest unpredictable for real-time inference.