Cyclone® 10 LP FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

Device Information

Interface Protocol

Design Planning

Design Entry

Simulation and Verification

Implementation and Optimization

Timing Analysis

On-Chip Debug

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Cyclone® 10 LP
Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook
Cyclone® 10 LP Device Datasheet
Cyclone® 10 LP Device Design Guidelines
Cyclone® 10 LP Device Overview
Cyclone® 10 LP Device Family Pin Connection Guidelines
LVDS SERDES Transmitter / Receiver IP Cores User Guide
FPGA Parallel Flash Loader IP Core User Guide
Altera® ASMI Parallel II IP Core User Guide
Altera® ASMI Parallel IP Core User Guide
Altera® Remote Update IP Core User Guide
AN 447: Interfacing FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
AN 496: Using the Internal Oscillator IP Core
AN 522: Implementing Bus LVDS Interface in Supported FPGA Device Families
AN 731: Simultaneous Switching Noise Guidelines for Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
AN 370: Using the FPGA Serial Flash Loader with the Quartus® Prime Software

2. Interface Protocol

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Ethernet
FPGA IP for Ethernet - Support Center

User Guides
PCI Express*
FPGA IP for PCI Express – Support Center

User Guides
Digital Signal Processing (DSP)
FPGA CORDIC IP Core User Guide
BCH IP Core User Guide
FFT IP Core User Guide
FIR II IP Core User Guide
Viterbi IP Core User Guide
Turbo IP Core User Guide
Floating-Point IP Cores User Guide
High-Speed Reed-Solomon IP Core User Guide
Reed-Solomon II IP Core User Guide
Random Number Generator IP Core User Guide

Training and Videos
External Memory Interface
Guide for New External Memory Interface (EMIF) Spec Estimator

3. Design Planning

Documentation

Training and Videos
Fast & Easy I/O System Design with Interface Planner

4. Design Entry

Documentation

The Quartus® Prime Software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

Quartus® Prime Standard Edition User Guide: Design Recommendations

User Guides / Device Overview / Device Datasheet / White Paper
Quartus® Prime Standard Edition Handbook Volume 1 Design and Synthesis

Design Examples
Platform Designer Pro Tutorial Design Example for Arria® 10 FPGA (.zip)
Platform Designer Tutorial Design Example for Arria® 10 FPGA (.zip)
Platform Designer Tutorial Design Example (.zip)

Training and Videos
Using the Quartus® Prime Standard Edition Software: An Introduction
Introduction to Verilog HDL
Verilog HDL Basics
Verilog HDL Advanced
SystemVerilog with Quartus® Prime Design Software
VHDL Basics
Introduction to Platform Designer
Platform Designer in the Quartus® Prime Pro Edition Software
Creating a System Design with Platform Designer: Getting Started
Using the Quartus® Prime Pro Edition Synthesis Engine

Software Downloads
Download center for all versions of the Quartus® Prime software

5. Simulation and Verification

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Quartus® Prime Standard Edition User Guide: Third-party Simulation
Simulating the a8237 Model with the Visual IP Software
Avalon® Verification IP Suite User Guide
FPGA Software Installation and Licensing
Simulating the a8251 Model with the Visual IP Software
Simulating the Reed-Solomon Model with the Visual IP Software
Simulating the Turbo Encoder/Decoder Model with the Visual IP Software
AN 811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Stratix® 10 Devices
AN 720: Simulating the ASMI Block in Your Design
AN 351: Simulating Nios® II Processor Designs
AN 508: Cyclone® III Simultaneous Switching Noise (SSN) Design Guidelines
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
Simulating Altera® Devices with IBIS Models
Simulating FPGA Designs

Design Examples
Avalon® Verification IP Suite Design Example

Training and Videos
Advanced System Design Using Platform Designer: System Verification with System Console
Advanced System Design Using Platform Designer: Component & System Simulation
Design Software Online Demonstration
Verifying Memory Interfaces IP in Altera® FPGA Devices

Software Downloads
Quartus® Software

6. Implementation and Optimization

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Quartus® Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization
Cyclone® 10 LP Device Design Guidelines

Training and Videos
Design Block Reuse in the Quartus® Prime Pro Software
Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Design Partitioning
Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Introduction
Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Timing Closure & Tips

7. Timing Analysis

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Timing Analysis Overview
Quartus® Prime Timing Analyzer Cookbook
AN 366: Understanding I/O Output Timing for Altera® Devices
AN 471: High-Performance FPGA PLL Analysis with TimeQuest
AN 433: Constraining and Analyzing Source-Synchronous Interfaces
AN 775: I/O Timing Information Generation Guidelines

Design Examples
Timing Analyzer Design Examples

Training and Videos
Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer
Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections
Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints
Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces
Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions
Getting Started with the TimeQuest Timing Analyzer
Timing Analysis: Lecture
Timing Analysis: Hands-on Labs
FPGA Timing Closure: Lecture
FPGA Timing Closure: Hands-On Lab

8. On-Chip Debug

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Design Debugging Using In-System Sources and Probes
FPGA Virtual JTAG (FPGA_virtual_jtag) IP Core User Guide
FPGA-Adaptive Software Debug and Performance Analysis
System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug
ByteBlaster II Download Cable User Guide
FPGA USB Download Cable User Guide
FPGA Download Cable II User Guide
EthernetBlaster Communications Cable User Guide
BSDL Support
AN 827: Unified Tool for Generating Programming Files
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems ,Design files
AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer
AN 693: Remote Hardware Debugging over TCP/IP for Altera SoC
AN 541: SerialLite II Hardware Debugging Guide
AN 543: Debugging Nios® II Software Using the Lauterbach Debugger
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
AN 624: Debugging with System Console over TCP/IP

Training and Videos
Debugging JTAG Chain Integrity
On-Chip Debugging of Memory Interfaces IP in Altera® FPGA Devices
JTAG Chain Debugger Tool
Quick Signal Tapping with SignalProbe in the Quartus® II Software

Software Downloads
FPGA Programming Software
Cable and Adapter Drivers Information
Quartus® Prime Software Stand-Alone Programmer

Knowledge Base Solution

Search the Knowledge Base for Cyclone® 10 LP Devices