FPGA Ethernet Support Center

Guidelines, tutorials and documentation for selecting a design, implementing ethernet links, and instructions on how to bring up your system and debug the links.

1. Device and IP Selection 2. Design Flow and IP Integration 3. Board Design and Power Management 4. Design Examples and Reference Designs 5. Debug 6. Training Courses and Videos

The Ethernet IP Support Center provides information on how to select, design, and implement Ethernet links for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices. There are also guidelines on how to bring up your system and debug the Ethernet links. This page is organized into categories that align with an Ethernet system design flow from start to finish.

Get additional support for Agilex™ 7 FPGA Interface Protocol Design, Agilex™ 5 FPGA Interface Protocol Design, and Agilex™ 3 FPGA Interface Protocol Design step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.

For other devices, search the Device and Product Support Collections.

Getting Started

Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

Agilex™ 7 Device Schematic Review Worksheet

Agilex™ 5 FPGAs and SoCs PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN)

Agilex™ 5 Device Schematic Review Worksheet

PCB Layout, Routing, and Power Distribution Network Design Guidelines: Agilex™ 3 FPGAs and SoCs

Watch the Ethernet getting started video

Ethernet Design Implementation Block Diagram

1. Device and IP Selection

Which FPGA Family Should I Use?

Refer to Table 1 to understand the Ethernet intellectual property (IP) core support for Agilex™, Stratix® 10, Arria® 10, and Cyclone® 10 devices. Compare between the four devices to select the right device for your Ethernet subsystem implementation.

Table 1 - Device and IP Core Support

Device Family	Tile Type (Agilex™ 7 device only)	IP Core	Electrical Interface	Forward Error Correction	1588 Precision Time Protocol	Auto Negotiation/ Link Training
Agilex™ 7	E-Tile	E-Tile Hard IP for Ethernet FPGA IP User Guide E-tile Hard IP Agilex™ 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration	100GBASE-KR4 100GBASE-CR4 CAUI-4 CAUI-2 25GBASE-KR 25GBASE-CR 25GBASE-R AUI 25GBASE-R Consortium Link 10GBASE-KR 10GBASE-CR 10G-XAUI *Modulation scheme supported: NRZ and PAM4	Reed Solomon (528, 514) Reed Solomon (544, 514)	✓	✓
	F-Tile	F-Tile Triple-Speed Ethernet FPGA IP User Guide	10BASE-T 100BASE-T 1000BASE-T	X	✓	✓
	F-Tile	F-Tile Low Latency Ethernet 10G MAC FPGA IP User Guide	NBASE-T	X	✓	X
	F-Tile	F-Tile Ethernet Multirate FPGA IP User Guide	NBASE-T	Reed Solomon (528, 514) Reed Solomon (544, 514) Ethernet Technology Consortium RS(272, 258) BASE-R Firecode	✓	✓
	F-Tile	F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY FPGA IP User Guide	NBASE-T	NA	✓	✓
	F-Tile	F-Tile 25G Ethernet FPGA IP user guide	25GBASE-R, 25GBASE-SR	Reed Solomon (528, 514)	X	X
	F-Tile	F-Tile Low Latency 50G Ethernet FPGA IP User Guide	50GBASE-R2, 50GBASE-SR2	X	X	X
	F-Tile	F-Tile Low Latency 100G Ethernet FPGA IP User Guide	100GBASE-R4, 100GBASE-SR4	Reed Solomon (528, 514)	X	X
	F-Tile	F-Tile Ethernet FPGA Hard IP User Guide F-Tile Ethernet FPGA Hard IP Design Example User Guide	10GBASE-KR, 10GBASE-CR 10GBASE-LR, 25GBASE-KR 25GBASE-CR, 25GBASE-R, 25GAUI-1, 40GBASE-KR4 40GBASE-CR4, 40GBASE-SR4, 50GBASE-KR1, 50GBASE-CR1, 50GBASE-KR2, 50GBASE-CR2,50GAUI-1, 50GAUI-2, 100GBASE-KR1, 100GBASE-CR1, 100GBASE-KR2, 100GBASE-CR2, 100GBASE-KR4, 100GBASE-CR4, 100GAUI-1, 100GAUI-2100GAUI-4, CAUI-2, CAUI-4, 200GBASE-KR2, 200GBASE-CR2, 200GBASE-KR4, 200GBASE-CR4, 200GAUI-2200GAUI-4, 200GAUI-8, 400GBASE-KR4, 400GBASE-CR4, 400GAUI-4, 400GBASE-KR8, 400GBASE-CR8, 400GAUI-8 *Modulation scheme supported: NRZ and PAM4	BASE-R Firecode Reed Solomon (528, 514) Reed Solomon (544, 514) Ethernet Technology Consortium RS(272, 258)	✓	✓
	F-Tile	Ethernet Subsystem FPGA IP User Guide	10GBASE-KR, 10GBASE-CR, 10GBASE-R, 25GBASE-KR, 25GBASE-CR, 25GBASE-R AUI, 25GBASE-R Consortium Link, 40GBASEKR-4, 40GBASE-CR4, 40GBASE-SR4, 50GBASE-KR2, 50GBASE-CR2, 50GAUI-2, 50GAUI-1, 100GBASE-KR4 , 100GBASE-CR4, CAUI-4, CAUI-2, CAUI-1, 200GAUI-4 , 200GAUI-2 , 200GAUI-8, 400GAUI-8, 400GAUI-4	KP-FEC Reed Solomon (544,514) Ethernet Technology Consortium RS(272, 258)	✓	✓
Device Family	IP Core		Electrical Interface	Forward Error Correction	1588 Precision Time Protocol	Auto Negotiation / Link Training
Agilex™ 5	GTS Ethernet FPGA Hard IP User Guide: Agilex™ 5 FPGAs and SoCs		25GBASE-KR 25GAUI-1 25GBASE-CR 10GBASE-KR 10GBASE-CR 10GBASE-LR	BASE-R Firecode (CL74) Reed-Solomon RS (528,514) (CL108) Ethernet Technology Consortium RS (528,514)	✓	✓
	Triple-Speed Ethernet FPGA IP User Guide:Agilex™ 3 and Agilex™ 5 FPGAs and SoCs		10BASE-T 100BASE-T 1000BASE-T 1000BASE-X	X	✓	✓
	Low Latency Ethernet 10G MAC FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs		10BASE-T 100BASE-T 1000BASE-T 1000BASE-X 10GBASE-R NBASE-T MGBASE-T	X	✓	X
	1G/2.5G/5G/10G Multirate Ethernet PHY FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs		NBASE-T MGBASE-T	X	✓	✓
	Low Latency 40G Ethernet FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs		40G-BASE-R4	X	X	X
Device Family	IP Core		Electrical Interface	Forward Error Correction	1588 Precision Time Protocol	Auto Negotiation / Link Training
Agilex™ 3	GTS Ethernet FPGA Hard IP User Guide: Agilex™ 3 FPGAs and SoCs		10GBASE-KR 10GBASE-CR 10GBASE-LR	BASE-R Firecode (CL74)	✓	✓
	Triple-Speed Ethernet FPGA IP User Guide:Agilex™ 3 and Agilex™ 5 FPGAs and SoCs		10BASE-T 100BASE-T 1000BASE-T 1000BASE-X	X	✓	✓
	Low Latency Ethernet 10G MAC FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs		10BASE-T 100BASET 1000BASE-T 1000BASE-X 10GBASE-R NBASE-T MGBASE-T	X	✓	X
	1G/2.5G/5G/10G Multirate Ethernet PHY FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs		NBASE-T MGBASE-T	X	✓	✓
Device Family	Tile Type (Stratix® 10 device only)	IP Core	Electrical Interface	Forward Error Correction	1588 Precision Time Protocol	Auto Negotiation/ Link Training
Stratix® 10 GX/SX/MX/TX/DX	L-Tile and H-Tile	Triple Speed Ethernet FPGA IP core User Guide	10BASE-T 100BASET 1000BASE-T 1000BASE-X		✓	✓
	L-Tile and H-TIle	Low Latency Ethernet 10G MAC FPGA IP User Guide Low Latency Ethernet 10G MAC Stratix® 10 FPGA IP Design Example User Guide	10BASE-T 100BASET 1000BASE-T 1000BASE-X 10GBASE-R NBASE-T MGBASE-T	Firecode FEC	✓	✓
	L-Tile and H-Tile	10GBASE-R L- and H-Tile Transceiver PHY User Guide
	L-Tile and H-Tile	10GBASE-KR PHY Stratix® 10 10GBASE-KR PHY IP Core User Guide
	L-Tile and H-Tile	1G/2.5G/5G/10G Multi-rate Ethernet PHY V1G/2.5G/5G/10G Multi-rate Ethernet PHY Stratix® 10 FPGA IP User Guide
	L-Tile and H-Tile	Low Latency 40-Gbps Ethernet FPGA IP Stratix® 10 Low Latency 40-Gbps Ethernet FPGA IP User Guide Stratix® 10 Low Latency 40G Ethernet FPGA IP Design Example User Guide	40G-BASE-R4	Firecode FEC		✓
	H-Tile	FPGA H-Tile Hard IP for Ethernet Stratix® 10 Device H-Tile Hard IP Ethernet FPGA IP User Guide Stratix® 10 H-tile Hard IP for Ethernet FPGA IP Design Example User Guide	50G-BASE-R2 100G-BASE-R4			✓
	L-Tile and H-Tile	25G Ethernet Stratix® 10 FPGA IP Stratix® 10 5G Ethernet FPGA IP User Guide Stratix® 10 5G Ethernet Stratix® 10 FPGA IP Design Example User Guide	25GBASE-SR 10GBASE-R	Reed Solomon (528, 514)	✓
	L-Tile and H-Tile	Low Latency 100-Gbps Ethernet FPGA IP Stratix® 10 Low Latency 100G Ethernet FPGA IP Core User Guide Stratix® 10 Low Latency 100G Ethernet FPGA IP Design Example User Guide	100G-BASE-R4	Reed Solomon (528, 514)
	E-Tile	E-Tile Hard IP for Ethernet FPGA IP User Guide E-Tile Hard IP for Ethernet Stratix® 10 FPGA IP Design Example User Guide	100GBASE-KR4 100GBASE-KR2 100GBASE-CR4 100GBASE-CR2 CAUI-4 CAUI-2 25GBASE-KR 25GBASE-CR 25GBASE-R AUI 25GBASE-R Consortium Link 10GBASE-KR 10GBASE-CR XAUI *Modulation scheme supported: NRZ and PAM4	Reed Solomon (528, 514) Reed Solomon (544, 514)	✓	✓
Device Family	IP Core		Electrical Interface	Forward Error Correction	1588 Precision Time Protocol	Auto Negotiation/ Link Training
Arria® 10 GX/GT/SX	Triple Speed Ethernet FPGA IP core User Guide		10BASE-T 100BASET 1000BASE-T 1000BASE-X		✓	✓
	Low Latency Ethernet 10G MAC FPGA IP Core User Guide Low Latency Ethernet 10G MAC FPGA IP Design Example User Guide		10BASE-T 100BASET 1000BASE-T 1000BASE-X 10GBASE-R NBASE-T MGBASE-T	Firecode FEC	✓	✓
	10GBASE-R FPGA IP Core User Guide
	XAUI PHY FPGA IP Core User Guide
	1G/10GbE and 10GBASE-KR PHY FPGA IP Core User Guide
	1G/2.5G/5G/10G Multi-rate Ethernet PHY FPGA IP Core User Guide
	Low Latency 40 Gbps Ethernet FPGA IP Core user guide Low Latency 40 Gbps Ethernet FPGA IP Design Example User Guide		40G-BASE-R4	Firecode FEC	✓	✓
	Low Latency 100 Gbps Ethernet FPGA IP Core User Guide Low Latency 100 Gbps Ethernet FPGA IP Design Example User Guide		100G-BASE-R10 100G-BASE-R4	Reed Solomon (528, 514)	✓
	25 Gbps Ethernet FPGA IP IP Core User Guide 25 Gbps Ethernet FPGA IP Design Example User Guide		25G-BASE-R1	Reed Solomon (528, 514)	✓
	50 Gbps Ethernet FPGA IP IP Core User Guide 50 Gbps Ethernet FPGA IP Design Example User Guide		50G-BASE-R2
Device Family	IP Core		Electrical Interface	Forward Error Correction	1588 Precision Time Protocol	Auto Negotiation/ Link Training
Cyclone® 10 LP/GX	Triple Speed Ethernet FPGA IP IP core User Guide		10BASE-T 100BASET 1000BASE-T 1000BASE-X		✓	✓
Cyclone® 10 LP/GX	Cyclone® 10 GX Low Latency Ethernet 10G MAC FPGA IP User Guide		10GBASE-R		✓

Please refer to the respective user guides to understand and find out whether the various features listed in the table above are mutually exclusive. For example: FPGA IP for Low Latency 100 Gbps Ethernet (for Arria® 10 devices) does not allow you to enable the RS-FEC and 1588 PTP simultaneously.

2. Design Flow and IP Integration

Where Can I Find Information on IP Integration?

Refer to the Getting Started section of your chosen IP core user guide. You can also refer to the following documents for details:

Agilex™ Devices

Stratix® 10 Devices

AN 778: Stratix® 10 Transceiver Usage

Arria® 10 Devices

Which Ethernet IP Core Should I Use?

FPGA IP for Ethernet

The FPGA IP for Ethernet portfolio contains various IP types to support data rates from 10 Mbps to 100 Gbps. Ethernet IP solutions encompass the Media Access Controller and PHY IP core, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). For more information, refer to the following user guides:

Agilex™ Devices

Stratix® 10 Devices

Arria® 10 Devices

Cyclone® 10 Devices

3. Board Design and Power Management

Pin Connection Guidelines

Agilex™ Devices

Stratix® 10 Devices

Stratix® 10 GX, MX, TX, DX, and SX Device Family Pin Connection Guidelines

Arria® 10 Devices

Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Cyclone® 10 Devices

Cyclone® 10 GX Device Family Pin Connection Guidelines

Schematic Review

Agilex™ Devices

Stratix® 10 Devices

Stratix® 10 GX, MX, TX and SX Schematic Review Worksheet

Arria® 10 Devices

Arria® 10 GX, GT, and SX Schematic Review Worksheet

Cyclone® 10 Devices

Cyclone® 10 GX Schematic Review Worksheet

Board Design Guidelines

Early Power Estimator

Thermal Power Guidelines

AN 787: Stratix® 10 Thermal Modeling and Management

Power Sequencing Guidelines

AN 692: Power Sequencing Considerations for Agilex™ 7, Stratix® 10, Arria® 10 and Cyclone® 10 GX Devices

4. Design Examples and Reference Designs

Agilex™ 7 Devices

E-Tile Hard IP for Ethernet Agilex™ Devices
- FPGA IP Design Example User Guide
Triple-Speed Ethernet IP
- F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide
10G Ethernet IP
- F-Tile Low Latency Ethernet 10G MAC FPGA IP Design Example User Guide
25G Ethernet IP
- F-Tile 25G Ethernet FPGA IP Design Example User Guide
F-Tile Ethernet Hard IP
- F-Tile Ethernet FPGA Hard IP Design Example User Guide
- F-Tile Dynamic Reconfiguration Design Example User Guide

Stratix® 10 Devices

Triple-Speed Ethernet
- AN830: FPGA Triple Speed Ethernet and On Board PHY Chip Reference Design
1G/2.5G Ethernet
- 1G/2.5G Ethernet Design Example for Stratix® 10
10G Ethernet
- FPGA IP for Low Latency Ethernet 10G MAC design example user guide
40G Ethernet
- FPGA IP for Low Latency 40-Gbps Ethernet design example user guide
FPGA H-Tile Hard IP for Ethernet
- Design example user guide
100G Ethernet
- FPGA IP for Low Latency 100-Gbps Ethernet design example user guide
E-Tile Hard IP for Ethernet Stratix® 10
- FPGA IP Design Example User Guide

Arria® 10 Devices

5. Debug

Tools

Stratix® 10 Device Ethernet Link Inspector

Ethernet Link Inspector consists of two sub-tools:

Link Monitor - Allows you to continuously monitor health of Ethernet link(s) between Stratix® 10 device and the link partner. Some of the key features you can monitor are: Link status summary (CDR lock, RX recovered frequency, lane alignment lock etc..) MAC packet statistics, FEC statistics etc.
Link Analysis - Allows you to have transparency into the link bring up sequence (like Auto-negotiation, Link Training etc.) or any other event captured in the Signal Tap Logic Analyzer file. Configure & capture the Signal Tap Logic Analyzer file for given event and then use Link Analysis to import the captured event & study Stratix® 10 behavior during that event duration.

To access Ethernet Link Inspector for a specific Quartus® software version, please refer to the table below.

For IP and Device support use model, refer to section ‘1.2 Supported IP Cores and Devices’ in the relevant Ethernet Link Inspector user guide.

Tool Files	Quartus Software Version	User Guide
Stratix® 10 Ethernet Link Inspector STP Package for Quartus® Prime 19.1 Pro (this tool is integrated into Quartus 19.1+)	Quartus® software 19.1 and above (L, H, and E-Tiles)	Ethernet Link Inspector User Guide for Stratix® 10 Devices
Ethernet Link Inspector Package v4.1	Quartus® software 18.0 to 18.1.2 (L, H, and E-Tiles)	Ethernet Link Inspector User Guide Archives for Ethernet Link Inspector Packages v4.1 and v1.1
Ethernet Link Inspector Package v1.1	Quartus® software 17.1 and earlier (L and H-Tiles)	Ethernet Link Inspector User Guide Archives for Ethernet Link Inspector Packages v4.1 and v1.1

Intellectual Property (IP) Core Release Notes

Agilex™ Devices

E-Tile Hard IP for Ethernet Release Notes

Stratix® 10 Devices

Arria® 10 Devices

Cyclone® 10 Devices

Knowledge Base Solutions

Agilex™ Devices

Search the Knowledge Base (FPGA IP for Agilex™ FPGAs and SoC FPGAs)

Stratix® 10 Devices

Arria® 10 Devices

Cyclone® 10 Devices

FPGA Technical Training

Technical Training Catalog

6. Training Courses and Videos

FPGA Quick Videos

Additional Quick Videos

Topic	Description
How FPGA 1588 System Solution Work in Different Clock Mode	Learn about new 1588 system-level reference design using both the FPGA IP for10G Ethernet MAC with 10G BaseR PHY and software, which includes the PTP stack LinuxPTPv1.5, a preloader, a 10 Gbps Ethernet MAC driver, and a PTP driver.
Debug Techniques for an FPGA Nios® II Ethernet Design - Part 1	Learn about debugging techniques for Ethernet or Nios II processor designs.
Debug Techniques for an FPGA Nios II Ethernet Design - Part 2	Learn about debugging techniques for Ethernet or Nios II processor designs.
How to Debug FPGA Triple Speed Ethernet Auto Negotiation Issue	Learn how to use auto negotiation for synchronizing Ethernet peripherals.
How to Debug TSE Auto-Negotiation Issue	Learn how to debug triple-speed Ethernet link synchronization issues.
How to Migrate FPGA Triple Speed Ethernet to Arria® 10 Devices in Quartus® Software	Learn how to migrate IP cores to the Arria® 10 FPGA family using the FPGA IP for Triple-Speed Ethernet as an example.
Migration from legacy 10G Ethernet MAC IP to the new low latency 10G Ethernet MAC IP	Learn about the FPGA IP for Low Latency 10G Ethernet MAC and how to migrate from the legacy FPGA IP for 10G Ethernet MAC.
Networking Features Under UEFI Shell	Learn how to use the Ethernet features under the UEFI Shell after booting to the DXE phase.
Scalable 10G MAC + 1G/10G PHY with 1588 Design Example Hardware Demo	Watch a demonstration on the FPGA IP for 10G Ethernet MAC and the FPGA IP for 1G/10G PHY with the IEEE 1588 feature. Learn how to perform the design hardware test and how to modify the hardware tcl script to specify the purpose of the test.

Still Have Questions?

Get answers for the most common design issues.

Search the Knowledge Base

Products

High-Performance

Mid-Range

Power and Cost-Optimized

AI Development Tools

FPGA Design & Simulation Tools

Embedded Design Tools & Software

IP Development Tools

High-Performance

Mid-Range

Power and Cost-Optimized

Interfaces

Memory Controllers

Digital Signal Processing & AI

Soft Embedded Processors

Transceivers & Basic Functions

Solutions

Design

FPGA Development Tools

Embedded Tools

Add-On Development Tools

Design Hubs

Developer Centers

Training

FPGA Developer Site

Design Store

All FPGA Documentation

Support

About

Contact Us

FPGA Ethernet Support Center

Getting Started

1. Device and IP Selection

Which FPGA Family Should I Use?

Table 1 - Device and IP Core Support

2. Design Flow and IP Integration

Where Can I Find Information on IP Integration?

Which Ethernet IP Core Should I Use?

3. Board Design and Power Management

Pin Connection Guidelines

Schematic Review

Board Design Guidelines

Early Power Estimator

Thermal Power Guidelines

Power Sequencing Guidelines

4. Design Examples and Reference Designs

5. Debug

Tools

Intellectual Property (IP) Core Release Notes

Knowledge Base Solutions

FPGA Technical Training

6. Training Courses and Videos

FPGA Quick Videos

Still Have Questions?