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FPGA AI Suite

Overview

FPGA AI Inference Development Flow

This end-to-end AI workflow integrates hardware and software for deploying models on FPGAs: 

1. Model Optimization: OpenVINO™ converts pretrained models to IR files (.xml, .bin).

2. Compilation: FPGA AI Suite estimates area/performance or generates optimized architectures, then compiles network files into a .bin for FPGA and/or CPU.

3. Inference Runtime: The .bin file is loaded by your application at runtime via Inference Engine and FPGA AI APIs for memory and hardware scheduling.

4. Reference Designs: Sample designs show how to run inference on FPGA with x86, Arm, or hostless setups.

5. Software Emulation: Evaluate FPGA AI IP accuracy using OpenVINO plugin—no hardware required (Agilex 5 only).

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What's New in 25.3

New Features that Advance Edge AI Inference

  • DDR free mode enables instantaneous model switching, lower power, higher FPS
    • Example: 27% increase in FPS for RESNET-50 on Agilex 7 FPGA.
       

  • Agilex 3 Production support, also including hostless JTAG example design on the Agilex 3 C-Series dev kit.
  • One stop install: available as option in Quartus installer.

Benefits

High Performance

Agilex 7 FPGA M-Series can achieve a maximum theoretical performance of 88.5 INT8 TOPS, or 3,679 Resnet-50 frames per second at 90% FPGA utilization.

Low Total Cost of Ownership with Easy System Integration

Integrate AI IP with other system-level components to achieve smaller footprint, lower power, and latency.

AI Front End Support

Use your favorite AI front end such as TensorFlow, Caffe, PyTorch, MXNet, Keras, and ONNX.

Simple and Standard Flows

Create and add AI inference IP to current or new FPGA designs with Quartus Prime Software or Platform Designer.

Access to Pre-Trained Models

FPGA AI Suite supports most of the models in Open Model Zoo.

Seamless Pre-Trained Model Conversion

OpenVINO Toolkit converts models from most of the standard frameworks to intermediate representations.

Push-Button Optimized AI IP Generation

FPGA AI Suite seamlessly generates optimal AI inference IP from pre-trained AI model sweeping the design space for optimal resources to performance targets.

Hardware-less Early Model Validation

Bit-accurate software emulation of the AI inference IP is available through the OpenVINO plugin interface enabling quicker evaluation of the accuracy of the model without hardware.

System Level Architectures

FPGA AI Suite is flexible and configurable for a variety of system-level use cases. Figure 1. lists the typical ways to incorporate the FPGA AI Suite IP into a system. The use cases span different verticals, from optimized embedded platforms to applications with host CPUs to data center environments with processors. It supports hostless designs and soft processors such as the Nios® V processors.
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CPU offload

AI Accelerator
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Multi-function CPU offload

AI Accelerator + Additional Hardware Function
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Ingest / Inline Processing + AI

AI Accelerator + Direct Ingest and Data Streaming
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Embedded SoC FPGA + AI

AI Accelerator + Direct Ingest and Data Streaming + Hardware Function + Embedded Arm or Nios® V Processors

Getting Started with the FPGA AI Suite

  1. Download the OpenVINO Toolkit 

    FPGA AI Suite requires the OpenVINO toolkit for design and development.

  2. Purchase FPGA AI Suite Unlimited Inferences from DigiKey or Mouser

    This option allows you to run unlimited inferences on hardware.

    Ordering code: SW-FPGAAISUITE

  3. Download FPGA AI Suite Limited Inferences

    This option allows you to run limited inferences on hardware without purchase.

  4. Browse Documentation

    Get user guides, release notes, and more.