banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by
Serial
By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

100G UDP IP Stack

Logic Fruit’s 100G UDP IP Stack – Optimized for high-speed 100G data transfer with minimal CPU dependency. Fully supports ARP and ICMP for reliable network connectivity and easy integration into SoC designs

View Details Right arrow Right arrow
/

ARINC 429 IP Core

Logic Fruit's ARINC 429 IP Core is a multichannel module with support for virtually any number of transmitters and Receivers. Both low speed (12.5 Kbps) and high speed (100 Kbps) data rates are supported for data transmission, along with other configurable data rates from 12.5 Kbps to 1 Mbps.

View Details Right arrow Right arrow
/

ARINC 818 IP CORE

ARINC 818 (ADVB) is a high data rate video bus based on the ANSI Fiber Channel Audio-Video (FC-AV) protocol standards. Emphasizing cost reduction as well as speeding up the link initialization. ARINC 818 is a unidirectional interface that was developed for avionics systems, such as connecting mission processors to cockpit displays like HUDS, MFDs, PFDs, or HMDs. Used widely in Boeing 787 and the KC46A tanker, Airbus A350 and A400M, the COMAC C-919, the C-17, F15, F18 and various military aircrafts.

View Details Right arrow Right arrow
/

Clock to PPS

Clock to Pulse Per Second Converter

View Details Right arrow Right arrow
/

CoaXPress Host IP Core

IP Core for CoaXPress host/receiver applications with speed support from 1 Gbps up to 100 Gbps.

View Details Right arrow Right arrow
/

CoaXPress-over-Fiber Bridge Device IP core

Bridge IP Core for CoaXPress protocol to use Ethernet physical layer for data transfer.

View Details Right arrow Right arrow
/

CSENT-Rx: SENT/SAE J2716 Receiver

The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous sensors. It can be used for receiving data from one or multiple sensors using a single SENT line. The CSENT-RX provides access to its control, status, and data registers via a 32-bit APB, or AXI4-Lite bus interface. The core provides a glitch filter on the serial data input and has data mapping functionality on received data to offload the connected host from data formatting. The received data are accessible via the register interface. The core is also capable of generating trigger pulses requesting synchronous sensors to send data. A set of handshaking signals facilitates the integration with an external DMA controller. The CSENT-RX core is designed with industry best practice, has been rigorously verified and is production proven.

View Details Right arrow Right arrow
/
Offerings Image

Current: xSPI Initiator core.  

xSPI Memory Controller Core for PSRAM, NOR Flash, STT-MRAM. Protocols: (a) JEDEC xSPI Profile 1.0, 2.0; (b) HyperBus 1.0, 2.0, 3.0; (c) OctaBus; (d) Octal Bus; (e) Exccela Bus. SLL support x8 and x16 PSRAM devices, and support chaining two x16 PSRAM devices to create x32 PSRAM channel.

View Details Right arrow Right arrow
/

CXL 3 CONTROLLER IP

The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for advanced systems. It supports multiple channels and configurable CXL degraded modes, ensuring seamless integration with CXL devices and enabling high-performance data transfer. Ideal for versatile system designs, it accommodates all three CXL device types to facilitate efficient connectivity and scalable architecture.

View Details Right arrow Right arrow
/
Listing 9 out of 72 Offerings