The Quartus® Prime Design Software Suite encompasses all software design tools needed to bring your FPGA from concept to production. The topics on this web page will guide you through all of the Quartus® Prime software features. Select your area of interest and navigate to the specific resources you need in the Quartus® Prime design flow.

• Quartus® Prime Software Quick Start Guide
  • A brief guide on how to set up a project, compile, perform timing analysis, and program an FPGA device.
• Read Me First! (ORMF1000)
  • A 44-minute free online course. This course is a starting point to quickly understand and use FPGA products, collateral, and resources.
• Download the Quartus® Prime software
• Get a license to run the Quartus® Prime software

Many more training courses are available. For a full catalog, go to FPGA Training.

I/O planning is done at an early stage in FPGA design to ensure a successful placement in your target device while meeting dedicated pin and timing constraints.
 

• The Quartus® Prime Pro Edition software offers two tools to manage the complex process of meeting the many constraints of I/O placement.
   

I/O Planning Documentation

Software Tool Documentation

• Managing Device I/O Pins chapter in a section of the Quartus® Prime Pro Edition User Guide
• Interface Planning chapter in a section of the Quartus® Prime Pro Edition User Guide

Device Documentation

• Pin-Out Files for Altera® FPGA Devices
• Pin Connection Guidelines - per device Family

Other Resources

I/O planning involves many considerations especially when high-speed I/Os or specific protocols are involved.

For more information on I/O management and board development support, visit:

• I/O Management and Board Development Support Center
• Signal Integrity Analysis Resource Center

Design Entry - Overview

You can express your design using several design entry methods:

• Using a hardware description language (HDL)
• Verilog
• SystemVerilog
• VHDL
• Platform Designer, a graphical entry tool for connecting complex modules in a structured way
• Other high-level entry methods
• High Level Synthesis (HLS) using C++ to express complex modules
• OpenCL™ uses C++ to implement computational algorithms across heterogeneous platforms

FPGA Intellectual Property

In addition to direct design entry, FPGAs support a large portfolio of intellectual property (IP) designed specifically for use in FPGAs.

Using HDL Templates

The Quartus® Prime software offers several templates for commonly used logic elements such as registers, selected signal assignments, concurrent signal assignments, and subprogram calls. Templates are available in Verilog, SystemVerilog, and VHDL.

If you are unsure of the best way to write a specific function to ensure that it will be implemented correctly, you should refer to these templates. The template system is fully described in the Inserting HDL Code from a Provided Template section in the Design Recommendations User Guide.

Recommended HDL Coding Style

HDL coding styles have a significant effect on the quality of results for logic designs. Synthesis tools will optimize the design, but to achieve precise results, you need to code in a style, which will be readily recognized by the synthesis tool as specific logic constructs.

In addition, there are good design practices, which should be followed for general digital logic design and for LAB-based devices in particular. Managing logic reset methodologies, pipeline delays, and proper synchronous signal generation are some examples of good digital design practices. Some resources for learning good HDL coding practices are listed below.

Resources for Good HDL Coding Style Guidelines

Intellectual Property

Altera® FPGAs support a large portfolio of intellectual property (IP) designed specifically for use in FPGAs. Each IP includes a simulation model for design verification before device implementation. See the following links for more information on available IP cores and the IP ecosystem within the Quartus® Prime software.

Platform Designer

Simulation Overview

The Quartus® Prime software supports RTL and gate-level design simulation in supported EDA simulators.

Simulation involves:

• Setting up your simulator working environment
• Compiling simulation model libraries
• Running your simulation

The Quartus® Prime software supports the use of a scripted simulation flow to automate simulation processing in your preferred simulation environment.

In the Quartus® Prime Standard Edition software, you have the option of using the NativeLink tool flow, which automates the launch of your chosen simulator.

NativeLink Simulation Flow

In the Quartus® Prime Standard Edition software, you have the option of using NativeLink. This lets you automatically launch all the steps needed to simulate your design after modifying your source code or IP.

The NativeLink feature integrates your EDA simulator with the Quartus® Prime Standard Edition software by automating the following:

• Generation of simulator-specific files and simulation scripts.
• Compilation of simulation libraries.
• Automatic launching of your simulator following the Quartus® Prime software analysis and elaboration, analysis and synthesis, or after a full compilation.

Resources for NativeLink Simulation Setup

Synthesis Overview

The Logic Synthesis stage of the Quartus® software design flow will take the register transfer level (RTL) code and create a netlist of lower level primitives (the post-synthesis netlist). The post-synthesis netlist will then be used as an input to the Fitter, which will place and route the design.

The Quartus® Prime and Quartus® II software include advanced integrated synthesis and interfaces with other third-party synthesis tools. The software also offers schematic netlist viewers that you can use to analyze a structure of a design and see how the software interpreted your design.

Synthesis results can be viewed with the Quartus® Netlist viewers, both after RTL elaboration and after Technology Mapping.

Synthesis Documentation

Synthesis Training and Demonstrations

High-Level Synthesis

The High-Level Synthesis (HLS) tool takes in a design description written in C++ and generates RTL code that is optimized for Altera® FPGAs.

For more information on the HLS Compiler, including documentation, examples, and training courses, view the HLS Support Page.

Fitter - Pro Edition

With the Quartus® Prime Pro Edition software, the Fitter does its work in individually controllable stages; you can optimize each stage individually by running just that stage of the fitter process, iterating to optimize that stage.

By default, the Fitter will run through all its stages. However, you can analyze the results of Fitter stages to evaluate your design before running the next stage, or before running a full compilation. For more information on how to use the Fitter stages to control the quality of results for your design, refer to the Running the fitter section in the compiler user guide: Quartus® Prime Pro edition.

You can specify several settings to direct the effort level of the Fitter for such things as register packing, register duplication and merging, and overall effort level. For more information on Fitter settings, see discussions under the Fitter settings reference section in the compiler user guide: Quartus® Prime Pro edition.

Fitter - Standard Edition

In the Quartus® Prime Standard Edition software, you can specify several settings to direct the effort level of the Fitter such as register packing, register duplication and merging, and overall effort level. For a complete listing of Fitter Settings, see Compiler Settings Help Page

For more information on Fitter settings, see discussions under

• Reducing compilation time section of the Quartus® Prime standard edition user guide: Compiler.
• Timing closure and optimization section of the Quartus® Prime standard edition user guide: Design optimization.

Timing Analysis Overview

The Timing Analyzer determines the timing relationships that must be met for the design to correctly function and checks arrival times against required times to verify timing.

Timing analysis involves many foundational concepts: asynchronous v. synchronous arcs, arrival and required times, setup and hold requirements, etc. These are defined in the Timing Analysis Basic Concepts section of the Quartus® Prime Standard Edition User Guide: Timing Analyzer.

The Timing Analyzer applies your timing constraints and determines timing delays from the results of the Fitter's implementation of your design into the target device.

The Timing Analyzer must operate from an accurate description of your timing requirements, expressed as timing constraints. The Constraining Designs section of the Quartus® Prime Standard Edition User Guide: Timing Analyzer describes how timing constraints can be added to.sdc files, for use by both the Fitter and the Timing Analyzer.

Timing closure is an iterative process of refining timing constraints; adjusting parameters for synthesis and the Fitter, and managing fitter seed variations.

Timing Closure

If the Timing Analyzer determines that your timing specifications are not met, then the design must be optimized for timing until the discrepancy is closed and your timing specifications are met.

Timing closure involves several possible techniques. The most effective techniques will vary with each design. The Timing Closure and Optimization chapter in the Design Optimization User Guide: Quartus® Prime Pro Edition gives a lot of practical advice about the timing closure process.

There are several additional training courses to help you understand how to evaluate your design for the right timing closure techniques.

Design Optimization Overview

The Quartus® Prime and Quartus® II software include a wide range of features to help you optimize your design for area and timing. This section provides the resources to help you with design optimization techniques and tools.

The Quartus® Prime and Quartus® II software offer physical synthesis netlist optimization to optimize designs further than the standard compilation process. Physical synthesis helps improve the performance of your design, regardless of the synthesis tool used.

Design Optimization Training Courses

Design Optimization Tools

The Quartus® Prime software provides tools that present your design in visual ways. These tools let you diagnose any problem areas in your design, in terms of logical or physical inefficiencies.

• You can use the Netlist Viewers to see a schematic representation of your design at several stages in the implementation process: before synthesis, after synthesis, and after place-and-route. This enables you to confirm your design intent at each stage.
• The Design Partition Planner helps you visualize and revise a design's partitioning scheme by showing timing information, relative connectivity densities, and the physical placement of partitions. You can locate partitions in other viewers, or modify or delete partitions.
• With the Chip Planner, you can make floorplan assignments, perform power analysis, and visualize critical paths and routing congestion. The Design Partition Planner and the Chip Planner allow you to partition and layout your design at a higher level.
• Design Space Explorer II (DSE) automates the search for the settings that give the best results in any individual design. DSE explores the design space of your design, applies various optimization techniques, and analyzes the results to help you discover the best settings for your design.

Using these tools can help you optimize the implementation of the device.

Netlist Viewers

The Quartus® Prime software netlist viewers provide powerful ways to view your design at various stages. Cross probing is possible with other design views: you can select an item and highlight it in the Chip Planner and Design File Viewer windows.

• The RTL Viewer shows the logic and connections inferred by the synthesizer, after elaboration of the hierarchy and major logic blocks. You can use the RTL Viewer to check your design visually before simulation or other verification processes.
• The Technology Map Viewer (Post-Mapping) can help you locate nodes in your netlist after synthesis but before place-and-route.
• The Technology Map Viewer (Post-Fitting) shows the netlist after place-and-route. This can differ from the Post-Mapping netlist because the fitter may make optimizations in order to meet constraints during physical optimization.

Netlist and Finite State Machine Viewers

See a demonstration of the Quartus® software Netlist Viewer and Finite State Machine Viewer in the videos below.

Quartus® Prime Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs (part 1)

The Quartus® Prime RTL Viewer and State Machine Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.

Quartus® Prime Netlist Viewers: Tools That Help Analyzing and Debugging Your Designs (part 2)

The Quartus® Prime RTL Viewer and State Machine Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.

Netlist Viewers Resources

Chip Planner

Design floorplan analysis helps to close timing and ensure optimal performance in highly complex designs. The Chip Planner in the Quartus® Prime software helps you close timing quickly on your designs. You can use the Chip Planner together with Logic Lock Regions to compile your designs hierarchically and assist with floorplanning. Additionally, use partitions to preserve placement and routing results from individual compilation runs.

You can perform design analysis as well as create and optimize the design floorplan with the Chip Planner. To make I/O assignments, use the Pin Planner.

Chip Planner resources.

Design Space Explorer II

Design Space Explorer II (DSE) allows you to explore the many parameters available for design compilation.

You can use the DSE to manage multiple compilations with different parameters to find the best combination of parameters that allow you to achieve timing closure.

Design Space Explorer II resources.

As FPGAs increase in performance, size, and complexity, the verification process can become a critical part of the FPGA design cycle. To alleviate the complexity of the verification process, Altera® provides a portfolio of on-chip debugging tools. The on-chip debugging tools allow real-time capture of internal nodes in your design to help you verify your design quickly without the use of external equipment, such as a bench logic analyzer or protocol analyzer. This can alleviate the number of pins needed for board-level signal probing. For a guide to all the tools in the debug portfolio, refer to the System Debugging Tools section in the Debug Tools User Guide: Quartus® Prime Pro Edition.
 

On-Chip Debug Design Examples 

Here are some examples to help you leverage the available features for common debug scenarios.

• SignalTap* II State-Based Triggering Flow
• In-System Sources and Probes Example
• Transceiver Toolkit Examples for Stratix® V GX, Arria® V GX/GT, Cyclone® V GX/GT and Stratix® IV GX/GT Devices
• System Console Design Examples (.qar Quartus® software archive format)

Block-Based Design Flows

The Quartus® Prime Pro Edition design software offers block-based design flows. There are of two types- the Incremental Block-Based Compilation and Design Block Reuse flows, which allow your geographically diverse development team to collaborate on a design.

Incremental Block-Based Compilation is preserving or emptying a partition within a project. This works with core partitions and requires no additional files or floor planning. The partition can be emptied, preserved at Source, Synthesis, and Final snapshots.

The Design Block Reuse flow enables you to reuse a block of a design in a different project by creating, preserving, and exporting a partition. With this feature, you can expect a clean hand off timing-closed modules between different teams.

Block-Based Design Resources

• Block-Based design flow section in the Quartus® Prime Pro Edition User Guide
• AN 839: Design Block Reuse Tutorial: for Arria® 10 FPGA Development Board
• Design File (.zip)
• Training: Design Block Reuse (OBBDR100)
• Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Introduction
• Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Design Partitioning
• Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Timing Closure & Tips

Rapid Recompile

Rapid Recompile allows the reuse of previous synthesis and fitter results when possible, and does not reprocess unchanged design blocks. Rapid Recompile can reduce total compilation time after making small design changes. Rapid Recompile supports HDL-based functional ECO changes and enables you to reduce your compile time while preserving the performance of unchanged logic. Rapid Recompile - Support Resources

Partial Reconfiguration

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function.

You can create multiple personas for a region of your device, and reconfigure that region without impacting operations in areas outside that persona.

For more information on Partial Reconfiguration, see the Partial reconfiguration page.

Scripting

The Quartus® Prime and Quartus® II software includes comprehensive scripting support for command-line and tool command language (Tcl) script design flows. Separate executables for each stage of the software design flow, such as synthesis, fitting, and timing analysis, include options for making common settings and performing common tasks. The Tcl scripting application programming interface (API) includes commands covering basic to advanced functionality.

Command-Line Scripting

You can use Quartus® Prime or Quartus® II software command-line executables in batch files, shell scripts, makefiles, and other scripts. For instance, use the following command to compile an existing project:

$ quartus_sh --flow compile

Tcl Scripting

Use the Tcl API for any of the following tasks:

• Creating and managing projects
• Making assignments
• Compiling designs
• Extracting report data
• Performing timing analysis

You can get started with some of the examples in the Quartus® II software Tcl examples web page. Several other resources are listed below.

Scripting Resources

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