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10GBASE-R PHY FPGA IP
The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.
By Altera
Aurora 64B/66B IP Core
The ALSE Aurora 64B/66B is a complete and fully compliant implementation of the published protocol. It allows to interconnect Altera FPGAs to Altera and other vendors FPGAs through High-Speed Serial links, from 1Gb/s to 800 Gb/s.
By ALSE Advanced Logic Synthesis for Electronics
Aurora 8B/10B IP Core
The ALSE Aurora 8B/10B IP Core makes this open protocol available to all Altera FPGAs (that include transceivers).
By ALSE Advanced Logic Synthesis for Electronics
CPRI FPGA IP
Altera CPRI FPGA IP delivers a high-performance, standards-compliant implementation of the CPRI Specification V7.0, enabling reliable, high-speed communication between Radio Equipment Controllers (RECs) and Remote Radio Equipment (REs). Fully configurable as either REC or RE, the IP simplifies integration in remote radio network applications and accelerates deployment of robust, low-latency fronthaul links.
By Altera
ION 64b/66b High Speed Serial Interface IP
High-speed serial interface (13.5 Gbps maximum) with a lightweight protocol
By Macnica Americas
ION 8b/10b High Speed Serial Interface IP
High-speed serial interface (8 Gbps maximum) achieved using a lightweight protocol
By Macnica Americas
IPM-UNFC
NAND Flash controller up to ONFI 5.x compliant with an embedded hardware ECC (either IPM-BCH or IPM-LDPC)
By IP-Maker
JESD204 FPGA IP
Altera JESD204 IP is a high-performance, JEDEC-compliant interface solution designed to simplify and accelerate the integration of high-speed data converters with digital processing systems. Supporting data rates up to 32.44 Gbps, it efficiently manages the physical, data link, and transport layers while offering pre-verified design examples and intuitive configuration, significantly reducing development time. Its robust clock synchronization and interoperability features ensure reliable, standards-based performance across demanding applications.
By Altera
LVDS Tunneling Protocol and Interface IP
LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 specification to facilitate the tunneling of low-speed signals between the host platform module (HPM) and secure control module (SCM) through the low-voltage differential signaling (LVDS) interfaces.
By Altera